Hi All,
This works around an ICE in reload where from expand we get the following RTL
generated for VSTRUCT mode writes:
(insn 446 354 445 2 (set (reg:CI 383)
(subreg:CI (reg:V4SI 291) 0)) "small.i":146:22 3408 {*aarch64_movci}
(nil))
This sequence is trying to say two things:
1) liveliness: It's trying to say that eventually the whole CI reg will be
written to. It does this by generating the paradoxical subreg.
2) write data: It's trying to in the same instruction also write the V4SI mode
component at offset 0 in the CI reg.
Reload is unable to understand this concept and so it attempts to handle this
instruction by breaking apart the instruction, first writing the data and then
tries to reload the paradoxical part. This gets it to the same instruction
again and eventually we ICE since we reach the limit of no. reloads.
This patch fixes it by in the backend when we see such a paradoxical
construction breaking it apart and issuing a clobber to correct the liveliness
information and then emitting a normal subreg write for the component that the
paradoxical subreg was trying to write to.
Concretely we generate this:
(insn 42 41 43 (clobber (reg/v:CI 122 [ diD.5226 ])) "small.i":121:23 -1
(nil))
(insn 43 42 44 (set (subreg:V4SI (reg/v:CI 122 [ diD.5226 ]) 0)
(reg:V4SI 136)) "small.i":121:23 -1
(nil))
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master and back-port to GCC 9 and GCC 8 after some stew?
I will look into seeing if we can not generate these at all, but I'm not sure
this is possible since the mid-end would need both the Mode and the Class to
know that a pseudo will be assigned to multiple hardregs.
Thanks,
Tamar
gcc/ChangeLog:
2020-03-09 Tamar Christina <tamar.christ...@arm.com>
PR target/94052
* config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical
subregs of VSTRUCT modes.
gcc/testsuite/ChangeLog:
2020-03-09 Tamar Christina <tamar.christ...@arm.com>
PR target/94052
* gcc.target/aarch64/pr94052.C: New test.
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