Hi all,
The two affected SVE2 patterns in this patch output a movprfx'ed
instruction in their second alternative
but don't set the "movprfx" attribute, which will result in the wrong
instruction length being assumed by the midend.
This patch fixes that in the same way as the other SVE patterns in the
backend.
Bootstrapped and tested on aarch64-none-linux-gnu.
Committing to trunk.
Thanks,
Kyrill
2020-03-06 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
Specify movprfx attribute.
(@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
commit b9694320e1bfbfc92255b30cc108a81a243770c6
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date: Fri Mar 6 15:26:20 2020 +0000
[AArch64] Add movprfx attribute to a couple of SVE2 patterns
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index f82e60e25c7..e18b9fef16e 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -690,6 +690,7 @@
"@
<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>"
+ [(set_attr "movprfx" "*,yes")]
)
(define_insn "@aarch64_sve_<sve_int_op>_lane_<mode>"
@@ -706,6 +707,7 @@
"@
<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]
movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]"
+ [(set_attr "movprfx" "*,yes")]
)
;; -------------------------------------------------------------------------
