On Sun, 2020-03-01 at 00:43 +0900, Oleg Endo wrote: > > > This could well be a target issue. I haven't tried to debug it. If > > it's a > > target issue, I'm fully comfortable punting it to the SH folks for > > resolving. > > The R0_REGS spill failure is a general problem, in particular with old > reload. The atomic patterns tend to trigger it in one circumstance or > the other. The IRA change probably just stresses it more. Perhaps it > will go away with -mlra. > > However, LRA on SH still has its own issues, so it can't be generally > enabled by default yet, unfortunately. See also some of the recent > posts in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93877 It's almost certainly the case that the recent IRA changes are going to stress R0 more. If I'm reading what Vlad did correctly, one of the tie-breakers its using now is to choose the lowest numbered register when all else is equal. So R0 on SH is likely going to be more problematical.
I wonder if just reordering the regs on the SH (and adjusting the debug output to keep that working) would be enough to mitigate some of the R0 problems. And yes, I saw 93877 fly by too :( Jeff
