[PATCH 5/6] i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV

[H.J. Lu]

There is no need to set mode attribute to V16SFmode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

gcc/

        PR target/89229
        * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SF.
        * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
        for TYPE_SSEMOV.  Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
        and ext_sse_reg_operand check.

gcc/testsuite/

        PR target/89229
        * gcc.target/i386/pr89229-7a.c: New test.
        * gcc.target/i386/pr89229-7b.c: Likewise.
        * gcc.target/i386/pr89229-7c.c: Likewise.
---
 gcc/config/i386/i386.c                     |  6 +++++
 gcc/config/i386/i386.md                    | 26 ++--------------------
 gcc/testsuite/gcc.target/i386/pr89229-7a.c | 16 +++++++++++++
 gcc/testsuite/gcc.target/i386/pr89229-7b.c |  6 +++++
 gcc/testsuite/gcc.target/i386/pr89229-7c.c |  6 +++++
 5 files changed, 36 insertions(+), 24 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7a.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7c.c

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a6fe9894ab8..1d3b784532b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -5136,6 +5136,12 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands)
       else
        return "%vmovsd\t{%1, %0|%0, %1}";
 
+    case MODE_SF:
+      if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
+       return "vmovss\t{%d1, %0|%0, %d1}";
+      else
+       return "%vmovss\t{%1, %0|%0, %1}";
+
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 060a34c4bd4..b837c345f4e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3469,24 +3469,7 @@ (define_insn "*movsf_internal"
       return standard_sse_constant_opcode (insn, operands);
 
     case TYPE_SSEMOV:
-      switch (get_attr_mode (insn))
-       {
-       case MODE_SF:
-         if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
-           return "vmovss\t{%d1, %0|%0, %d1}";
-         return "%vmovss\t{%1, %0|%0, %1}";
-
-       case MODE_V16SF:
-         return "vmovaps\t{%g1, %g0|%g0, %g1}";
-       case MODE_V4SF:
-         return "%vmovaps\t{%1, %0|%0, %1}";
-
-       case MODE_SI:
-         return "%vmovd\t{%1, %0|%0, %1}";
-
-       default:
-         gcc_unreachable ();
-       }
+      return ix86_output_ssemov (insn, operands);
 
     case TYPE_MMXMOV:
       switch (get_attr_mode (insn))
@@ -3558,12 +3541,7 @@ (define_insn "*movsf_internal"
                  better to maintain the whole registers in single format
                  to avoid problems on using packed logical operations.  */
               (eq_attr "alternative" "6")
-                (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
-                                 (not (match_test "TARGET_AVX512VL")))
-                            (ior (match_operand 0 "ext_sse_reg_operand")
-                                 (match_operand 1 "ext_sse_reg_operand")))
-                         (const_string "V16SF")
-                       (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+                (cond [(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                             (match_test "TARGET_SSE_SPLIT_REGS"))
                          (const_string "V4SF")
                       ]
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7a.c 
b/gcc/testsuite/gcc.target/i386/pr89229-7a.c
new file mode 100644
index 00000000000..856115b2f5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7a.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512" } */
+
+extern float d;
+
+void
+foo1 (float x)
+{
+  register float xmm16 __asm ("xmm16") = x;
+  asm volatile ("" : "+v" (xmm16));
+  register float xmm17 __asm ("xmm17") = xmm16;
+  asm volatile ("" : "+v" (xmm17));
+  d = xmm17;
+}
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7b.c 
b/gcc/testsuite/gcc.target/i386/pr89229-7b.c
new file mode 100644
index 00000000000..93d1e43770c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7b.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
+
+#include "pr89229-7a.c"
+
+/* { dg-final { scan-assembler-times 
"vmovaps\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7c.c 
b/gcc/testsuite/gcc.target/i386/pr89229-7c.c
new file mode 100644
index 00000000000..e37ff2bf5bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7c.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+#include "pr89229-7a.c"
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
-- 
2.24.1