Hi Christophe,
On 01/23/2020 09:34 AM, Christophe Lyon wrote:
On Mon, 20 Jan 2020 at 19:01, Mihail Ionescu
<mihail.ione...@foss.arm.com> wrote:
Hi,
This patch fixes the scalar shifts tests added in:
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01195.html
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01196.html
By adding mthumb and ensuring that the target supports
thumb2 instructions.
*** gcc/testsuite/ChangeLog ***
2020-01-20 Mihail-Calin Ionescu <mihail.ione...@arm.com>
* gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c: Add mthumb and
target check.
* gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c: Likewise.
Is this ok for trunk?
Why not add a new entry in check_effective_target_arm_arch_FUNC_ok?
(there are already plenty, including v8m_main for instance)
Sorry for the delay, we were going to add the check_effective_target
to the MVE framework patches and then update this one. But I came
across some big endian issues and decided to update this now.
I've added the target check and changed the patch so it also
disables the scalar shift patterns when generating big endian
code. At the moment they are broken because the MVE shift instructions
have the restriction of having an even gp register specified first,
followed by the odd one, which requires swapping the data twice in
big endian. In this case, the previous code gen is preferred.
*** gcc/ChangeLog ***
2020-02-19 Mihail-Calin Ionescu <mihail.ione...@arm.com>
* config/arm/arm.md (ashldi3, ashrdi3, lshrdi3): Prevent scalar
shifts from being used on when big endian is enabled.
*** gcc/testsuite/ChangeLog ***
2020-02-19 Mihail-Calin Ionescu <mihail.ione...@arm.com>
* gcc.target/arm/armv8_1m-shift-imm-1.c: Add MVE target checks.
* gcc.target/arm/armv8_1m-shift-reg-1.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_v8_1m_mve_ok_nocache): New.
(check_effective_target_arm_v8_1m_mve_ok): New.
(add_options_for_v8_1m_mve): New.
Is this ok for trunk?
Christophe
Regards,
Mihail
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
index
5ffa3769e6ba42466242d3038857734e87b2f1fc..9822f59643c662c9302ad43c09057c59f3cbe07a
100644
--- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+/* { dg-options "-O2 -mthumb -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
long long longval1;
long long unsigned longval2;
diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
index
a97e9d687ef66e9642dd1d735125c8ee941fb151..a9aa7ed3ad9204c03d2c15dc6920ca3159403fa0
100644
--- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+/* { dg-options "-O2 -mthumb -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
long long longval2;
int intval2;
Regards,
Mihail
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index
0454908256727247b4d0a4f402ad234bdbf1907c..afc4e126a44cabd87001ea145c24c90700ac41f9
100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4399,7 +4399,7 @@
(match_operand:SI 2 "reg_or_int_operand")))]
"TARGET_32BIT"
"
- if (TARGET_HAVE_MVE)
+ if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN)
{
if (!reg_or_int_operand (operands[2], SImode))
operands[2] = force_reg (SImode, operands[2]);
@@ -4443,7 +4443,7 @@
"TARGET_32BIT"
"
/* Armv8.1-M Mainline double shifts are not expanded. */
- if (TARGET_HAVE_MVE
+ if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN
&& arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2])))
{
if (!reg_overlap_mentioned_p(operands[0], operands[1]))
@@ -4478,7 +4478,7 @@
"TARGET_32BIT"
"
/* Armv8.1-M Mainline double shifts are not expanded. */
- if (TARGET_HAVE_MVE
+ if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN
&& long_shift_imm (operands[2], GET_MODE (operands[2])))
{
if (!reg_overlap_mentioned_p(operands[0], operands[1]))
diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
index
9822f59643c662c9302ad43c09057c59f3cbe07a..883fbb092b18422e9109e3e87abab22f1c602fdb
100644
--- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mthumb -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
-/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mfloat-abi=softfp -mlittle-endian" } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
long long longval1;
long long unsigned longval2;
diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
index
a9aa7ed3ad9204c03d2c15dc6920ca3159403fa0..e125ff83c222fcf4cd5d929714ae118387b77273
100644
--- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mthumb -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
-/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mfloat-abi=softfp -mlittle-endian" } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
long long longval2;
int intval2;
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index
79166986c77b38b1ec99508a146ffd27d9725248..97107edeca870810cd851d6c05f4ed8cfc9b6e0d
100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4795,6 +4795,48 @@ proc
check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
return 0;
}
+# Return 1 if the target supports ARMv8.1-M MVE
+# instructions, 0 otherwise. The test is valid for ARM.
+# Record the command line options needed.
+
+proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
+ global et_arm_v8_1m_mve_flags
+ set et_arm_v8_1m_mve_flags ""
+
+ if { ![istarget arm*-*-*] } {
+ return 0;
+ }
+
+ # Iterate through sets of options to find the compiler flags that
+ # need to be added to the -march option.
+ foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard
-mfpu=auto"} {
+ if { [check_no_compiler_messages_nocache \
+ arm_v8_1m_mve_ok object {
+ #if !defined (__ARM_FEATURE_MVE)
+ #error "__ARM_FEATURE_MVE not defined"
+ #endif
+ } "$flags -mthumb"] } {
+ set et_arm_v8_1m_mve_flags "$flags -mthumb"
+ return 1
+ }
+ }
+
+ return 0;
+}
+
+proc check_effective_target_arm_v8_1m_mve_ok { } {
+ return [check_cached_effective_target arm_v8_1m_mve_ok \
+ check_effective_target_arm_v8_1m_mve_ok_nocache]
+}
+
+proc add_options_for_arm_v8_1m_mve { flags } {
+ if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
+ return "$flags"
+ }
+ global et_arm_v8_1m_mve_flags
+ return "$flags $et_arm_v8_1m_mve_flags"
+}
+
proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
