On Fri, Feb 07, 2020 at 09:00:40AM -0700, Jeff Law wrote: > On Thu, 2020-02-06 at 07:56 -0600, Segher Boessenkool wrote: > > On Wed, Feb 05, 2020 at 11:48:23AM -0700, Jeff Law wrote: > > > Yea, it's closely related. In your case you need to effectively ignore > > > the nop insn to get the optimization you want. In mine that nop insn > > > causes an ICE. > > > > > > I think we could take your cse bits + adding a !CALL_P separately from > > > the simplify-rtx stuff which Segher objected to. THat'd likely solve > > > the ARM ICEs and take you a tiny step forward on optimizing that SVE > > > case. Thoughts? > > > > CSE should consistently keep track of what insns are no-op moves (in its > > definition, all passes have a slightly different definition of this), > > and use that everywhere consistently. > So does that mean you object to the cse.c portion of Richard's patch?
It's more a "what we need to do in the future" thing, it is stage 4 now, it is too big a change to do now. What patch? The "34" patch? https://gcc.gnu.org/r278411 . I don't think each stanza of code should use it's own "noop-ness", no. I don't know if this patch makes matters worse or not. It doesn't seem suitable for stage 4 though. And Richard said the cse.c part breaks rs6000, if that is true, yes I do object ;-) Segher
