This patch addresses the concern the Segher raised in the original submission
of the patch to fix PR target/93569.  In addition to checking for D*-form
addresses in the traditional Altivec registers, this patch also checks for
D*-form addresses for vectors in the traditional floating point registers.
Neither one of these address forms were allowed before ISA 3.0 (power9).

I have done bootstraps on both little and big endian Linux 64-bit systems, and
there were no regressions for this change.  Can I check this patch into the
master branch?

https://gcc.gnu.org/ml/gcc-patches/2020-02/msg00387.html

2020-02-06  Michael Meissner  <meiss...@linux.ibm.com>

        PR target/93569
        * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
        we only had X-FORM (reg+reg) addressing for vectors.  Also before
        ISA 3.0, we only had X-FORM addressing for scalars in the
        traditional Altivec registers.

--- /tmp/VQDg8p_rs6000.c        2020-02-06 11:55:27.509363545 -0500
+++ gcc/config/rs6000/rs6000.c  2020-02-06 11:54:28.461531334 -0500
@@ -24923,7 +24923,8 @@ reg_to_non_prefixed (rtx reg, machine_mo
   unsigned size = GET_MODE_SIZE (mode);
 
   /* FPR registers use D-mode for scalars, and DQ-mode for vectors, IEEE
-     128-bit floating point, and 128-bit integers.  */
+     128-bit floating point, and 128-bit integers.  Before power9, only indexed
+     addressing was available for vectors.  */
   if (FP_REGNO_P (r))
     {
       if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode))
@@ -24936,16 +24937,20 @@ reg_to_non_prefixed (rtx reg, machine_mo
               && (VECTOR_MODE_P (mode)
                   || FLOAT128_VECTOR_P (mode)
                   || mode == TImode || mode == CTImode))
-       return NON_PREFIXED_DQ;
+       return (TARGET_P9_VECTOR) ? NON_PREFIXED_DQ : NON_PREFIXED_X;
 
       else
        return NON_PREFIXED_DEFAULT;
     }
 
   /* Altivec registers use DS-mode for scalars, and DQ-mode for vectors, IEEE
-     128-bit floating point, and 128-bit integers.  */
+     128-bit floating point, and 128-bit integers.  Before power9, only indexed
+     addressing was available.  */
   else if (ALTIVEC_REGNO_P (r))
     {
+      if (!TARGET_P9_VECTOR)
+       return NON_PREFIXED_X;
+
       if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode))
        return NON_PREFIXED_DS;
 

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

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