Matthew Malcomson <matthew.malcom...@arm.com> writes: > We take no action to ensure the SVE vector size is large enough. It is > left to the user to check that before compiling this intrinsic or before > running such a program on a machine. > > The main difference between ld1ro and ld1rq is in the allowed offsets, > the implementation difference is that ld1ro is implemented using integer > modes since there are no pre-existing vector modes of the relevant size. > Adding new vector modes simply for this intrinsic seems to make the code > less tidy. > > Specifications can be found under the "Arm C Language Extensions for > Scalable Vector Extension" title at > https://developer.arm.com/architectures/system-architectures/software-standards/acle > > gcc/ChangeLog: > > 2020-01-09 Matthew Malcomson <matthew.malcom...@arm.com> > > * config/aarch64/aarch64-protos.h > (aarch64_sve_ld1ro_operand_p): New. > * config/aarch64/aarch64-sve-builtins-base.cc > (class load_replicate): New. > (class svld1ro_impl): New. > (class svld1rq_impl): Change to inherit from load_replicate. > (svld1ro): New sve intrinsic function base. > * config/aarch64/aarch64-sve-builtins-base.def (svld1ro): > New DEF_SVE_FUNCTION. > * config/aarch64/aarch64-sve-builtins-base.h > (svld1ro): New decl. > * config/aarch64/aarch64-sve-builtins.cc > (function_expander::add_mem_operand): Modify assert to allow > OImode. > * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New > pattern. > * config/aarch64/aarch64.c > (aarch64_sve_ld1rq_operand_p): Implement in terms of ... > (aarch64_sve_ld1rq_ld1ro_operand_p): This. > (aarch64_sve_ld1ro_operand_p): New. > * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec. > * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New. > * config/aarch64/predicates.md > (aarch64_sve_ld1ro_operand_{b,h,w,d}): New. > > gcc/testsuite/ChangeLog: > > 2020-01-09 Matthew Malcomson <matthew.malcom...@arm.com> > > * gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: New test. > * gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: New test.
OK, thanks. Richard
