Hi Srinath,
On 11/14/19 7:13 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports following MVE ACLE intrinsics with unary operand.
vctp16q, vctp32q, vctp64q, vctp8q, vpnot.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for
more details.
[1]
https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
There are few conflicts in defining the machine registers, resolved by
re-ordering
VPR_REGNUM, APSRQ_REGNUM and APSRGE_REGNUM.
Regression tested on arm-none-eabi and found no regressions.
Ok for trunk?
Thanks,
Srinath.
gcc/ChangeLog:
2019-11-12 Andre Vieira <andre.simoesdiasvie...@arm.com>
Mihail Ionescu <mihail.ione...@arm.com>
Srinath Parvathaneni <srinath.parvathan...@arm.com>
* config/arm/arm-builtins.c (hi_UP): Define mode.
* config/arm/arm.h (IS_VPR_REGNUM): Move.
* config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
(APSRQ_REGNUM): Modify.
(APSRGE_REGNUM): Modify.
* config/arm/arm_mve.h (vctp16q): Define macro.
(vctp32q): Likewise.
(vctp64q): Likewise.
(vctp8q): Likewise.
(vpnot): Likewise.
(__arm_vctp16q): Define intrinsic.
(__arm_vctp32q): Likewise.
(__arm_vctp64q): Likewise.
(__arm_vctp8q): Likewise.
(__arm_vpnot): Likewise.
* config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
qualifier.
* config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
(mve_vpnothi): Likewise.
gcc/testsuite/ChangeLog:
2019-11-12 Andre Vieira <andre.simoesdiasvie...@arm.com>
Mihail Ionescu <mihail.ione...@arm.com>
Srinath Parvathaneni <srinath.parvathan...@arm.com>
* gcc.target/arm/mve/intrinsics/vctp16q.c: New test.
* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
############### Attachment also inlined for ease of reply
###############
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index
21b213d8e1bc99a3946f15e97161e01d73832799..cd82aa159089c288607e240de02a85dcbb134a14
100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -387,6 +387,7 @@ arm_set_sat_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define oi_UP E_OImode
#define hf_UP E_HFmode
#define si_UP E_SImode
+#define hi_UP E_HImode
#define void_UP E_VOIDmode
#define UP(X) X##_UP
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
485db72f05f16ca389227289a35c232dc982bf9d..95ec7963a57a1a5652a0a9dc30391a0ce6348242
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -955,6 +955,9 @@ extern int arm_arch_cmse;
#define IS_IWMMXT_GR_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <=
LAST_IWMMXT_GR_REGNUM))
+#define IS_VPR_REGNUM(REGNUM) \
+ ((REGNUM) == VPR_REGNUM)
+
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 102
@@ -999,7 +1002,7 @@ extern int arm_arch_cmse;
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ +1 VPR + 1 APSRQ + 1 APSRGE. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
#define FIRST_PSEUDO_REGISTER 107
@@ -1101,13 +1104,10 @@ extern int arm_regs_in_sequence[];
/* Registers not for general use. */ \
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
- SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, APSRGE_REGNUM, \
- VPR_REGNUM \
+ SP_REGNUM, PC_REGNUM, VPR_REGNUM, APSRQ_REGNUM,\
+ APSRGE_REGNUM \
}
-#define IS_VPR_REGNUM(REGNUM) \
- ((REGNUM) == VPR_REGNUM)
-
/* Use different register alloc ordering for Thumb. */
#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index
689baa0b0ff63ef90f47d2fd844cb98c9a1457a0..2a90482a873f8250a3b2b1dec141669f55e0c58b
100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -39,9 +39,9 @@
(LAST_ARM_REGNUM 15) ;
(CC_REGNUM 100) ; Condition code pseudo register
(VFPCC_REGNUM 101) ; VFP Condition code pseudo register
- (APSRQ_REGNUM 104) ; Q bit pseudo register
- (APSRGE_REGNUM 105) ; GE bits pseudo register
- (VPR_REGNUM 106) ; Vector Predication Register - MVE
register.
+ (VPR_REGNUM 104) ; Vector Predication Register - MVE
register.
+ (APSRQ_REGNUM 105) ; Q bit pseudo register
+ (APSRGE_REGNUM 106) ; GE bits pseudo register
]
)
;; 3rd operand to select_dominance_cc_mode
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
1d357180ba9ddb26347b55cde625903bdb09eef6..c8d9b6471634725cea9bab3f9fa145810b506938
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -192,6 +192,11 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a)
#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a)
#define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a)
+#define vctp16q(__a) __arm_vctp16q(__a)
+#define vctp32q(__a) __arm_vctp32q(__a)
+#define vctp64q(__a) __arm_vctp64q(__a)
+#define vctp8q(__a) __arm_vctp8q(__a)
+#define vpnot(__a) __arm_vpnot(__a)
#endif
__extension__ extern __inline void
@@ -703,6 +708,41 @@ __arm_vaddlvq_u32 (uint32x4_t __a)
return __builtin_mve_vaddlvq_uv4si (__a);
}
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp16q (uint32_t __a)
+{
+ return __builtin_mve_vctp16qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp32q (uint32_t __a)
+{
+ return __builtin_mve_vctp32qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp64q (uint32_t __a)
+{
+ return __builtin_mve_vctp64qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp8q (uint32_t __a)
+{
+ return __builtin_mve_vctp8qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vpnot (mve_pred16_t __a)
+{
+ return __builtin_mve_vpnothi (__a);
+}
Hmm, the spec says that this should generate:
VMSR P0,Rp
VPNOT
VMRS Rt,P0
but __builtin_mve_vpnothi will generate just a VPNOT... what's up with that?
Thanks,
Kyrill
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline void
diff --git a/gcc/config/arm/arm_mve_builtins.def
b/gcc/config/arm/arm_mve_builtins.def
index
aafcc2a4bede4e2f9f7845e60f30d4482b7f10bc..816b6dfca7fb221275212ca5f06fc6f679860a38
100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -1,5 +1,5 @@
/* MVE builtin definitions for Arm.
- Copyright (C) 2019 Free Software Foundation, Inc.
+ Copyright (C) 2019 Free Software Foundation, Inc.
Contributed by Arm.
This file is part of GCC.
@@ -71,3 +71,8 @@ VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si)
+VAR1 (UNOP_UNONE_UNONE, vctp16q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp32q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp64q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp8q, hi)
+VAR1 (UNOP_UNONE_UNONE, vpnot, hi)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index
9ad53e5655b01c26143a5f46c675658a450e0adf..ee2263e04309e8274ec76ae4478afb7cfba59f8f
100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -36,7 +36,7 @@
VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S
VMOVLBQ_S
VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
- VADDLVQ_U])
+ VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
@@ -54,6 +54,9 @@
(VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
(VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")])
+(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
+ (VCTP64Q "64")])
+
(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
@@ -71,6 +74,7 @@
(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
+(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w")
@@ -648,3 +652,31 @@
"vaddlv.<supf>32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
+
+;;
+;; [vctp8q vctp16q vctp32q vctp64q])
+;;
+(define_insn "mve_vctp<mode1>qhi"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
+ VCTPQ))
+ ]
+ "TARGET_HAVE_MVE"
+ "vctp.<mode1> %1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vpnot])
+;;
+(define_insn "mve_vpnothi"
+ [
+ (set (match_operand:HI 0 "s_register_operand" "=r")
+ (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "Up")]
+ VPNOT))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpnot"
+ [(set_attr "type" "mve_move")
+])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
new file mode 100644
index
0000000000000000000000000000000000000000..0530d23d6cb6283f19f9122bb85c22714eb71843
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve
-mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"}
} */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
new file mode 100644
index
0000000000000000000000000000000000000000..6e59362345a7b4e77028262c69bee42d230a6f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve
-mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"}
} */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
new file mode 100644
index
0000000000000000000000000000000000000000..9a9224ef88de71012373b0f0cebedbade045fccd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve
-mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"}
} */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
new file mode 100644
index
0000000000000000000000000000000000000000..3118d9b60a2eb8c72eb1273445a0b3370b603402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve
-mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"}
} */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
new file mode 100644
index
0000000000000000000000000000000000000000..9422d342b9d8bf024c2a95877c61e8dd0bd4ffb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve
-mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"}
} */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
+
+mve_pred16_t
+foo1 (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
