On 06/12/2019 17:57, Andrew Stubbs wrote:
Hi all,
I've committed the attached to fix a failure-to-assemble bug that can
occur in some vectorized code. This has been hidden for a long time
because sub-word vectors were disabled on GCN, but this is no longer the
case.
The gather load instructions had the suffixes for store, which didn't
assemble well. E.g. it had 'flat_load_short', instead of
'flat_load_ustore'.
That should have been "ushort".
This fixes about 39 tests in vect.exp.
And this patch does the same for 'global_load_ushort', which fixes the
same tests in the GCN5 multilibs.
Andrew
Fix more unrecognised GCN instructions
2019-12-09 Andrew Stubbs <a...@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Change
%s to %o in asm output.
(gather<mode>_insn_2offsets<exec>): Likewise.
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 95e0731a374..16b37e8daab 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -722,7 +722,7 @@
sprintf (buf, "flat_load%%o0\t%%0, %%1%s\;s_waitcnt\t0", glc);
}
else if (AS_GLOBAL_P (as))
- sprintf (buf, "global_load%%s0\t%%0, %%1, off offset:%%2%s\;"
+ sprintf (buf, "global_load%%o0\t%%0, %%1, off offset:%%2%s\;"
"s_waitcnt\tvmcnt(0)", glc);
else
gcc_unreachable ();
@@ -780,7 +780,7 @@
/* Work around assembler bug in which a 64-bit register is expected,
but a 32-bit value would be correct. */
int reg = REGNO (operands[2]) - FIRST_VGPR_REG;
- sprintf (buf, "global_load%%s0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
+ sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
"s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
}
else
