On 07/12/11 16:25, Richard Earnshaw wrote:
2011-12-06 Andrew Stubbs<a...@codesourcery.com>
gcc/
* config/arm/arm.md (one_cmpldi2): Rename to ...
(one_cmpldi2_core): ... this, and modify it to prevent it being
used for NEON.
(one_cmpldi2): New define_expand.
* config/arm/neon.md (one_cmpldi2_neon): New define_insn.
+(define_insn_and_split "*one_cmpldi2_core"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r")
+ (not:DI (match_operand:DI 1 "arm_general_register_operand" "0,r")))]
Thinking about it, for an operation with one input and one output, there's no
need for the
earlyclobber marker when the input is tied to the output (there's no other
operand that can be
clobbered).
Otherwise OK.
Thanks I'll test and commit the attached updated patch once stage 1
opens again.
Andrew
2011-12-07 Andrew Stubbs <a...@codesourcery.com>
gcc/
* config/arm/arm.md (one_cmpldi2): Rename to ...
(one_cmpldi2_core): ... this, and modify it to prevent it being
used for NEON.
(one_cmpldi2): New define_expand.
* config/arm/neon.md (one_cmpldi2_neon): New define_insn.
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4199,10 +4199,16 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
"")
-(define_insn_and_split "one_cmpldi2"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))]
+(define_expand "one_cmpldi2"
+ [(set (match_operand:DI 0 "s_register_operand" "")
+ (not:DI (match_operand:DI 1 "s_register_operand" "")))]
"TARGET_32BIT"
+ "")
+
+(define_insn_and_split "*one_cmpldi2_core"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "=r,&r")
+ (not:DI (match_operand:DI 1 "arm_general_register_operand" "0,r")))]
+ "TARGET_32BIT && !TARGET_NEON"
"#"
"TARGET_32BIT && reload_completed"
[(set (match_dup 0) (not:SI (match_dup 1)))
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -896,6 +896,20 @@
[(set_attr "neon_type" "neon_int_1")]
)
+(define_insn "*one_cmpldi2_neon"
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?r,?&r,?w")
+ (not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))]
+ "TARGET_NEON"
+ "@
+ vmvn\t%P0, %P1
+ #
+ #
+ vmvn\t%P0, %P1"
+ [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
+ (set_attr "length" "*,8,8,*")
+ (set_attr "arch" "nota8,*,*,onlya8")]
+)
+
(define_insn "abs<mode>2"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
