As we discussed in the V6 patches #1 and #2, before submitting the patches
adding eI support for movdi and movsi, you prefered that I reformat the patches
to make them easier in the future to identify the changes.
This patch changes just the movdi_internal64 insn. All of the constraints are
in the same order as the current sources. I did add setting "num_insns" to
this patch, but I left in setting "length". I found otherwise the Spec
benchmarks did not generate the same code with the patch.
I have bootstrapped the compiler with this change and the movdi_internal64
patch that will be submitted next, and there were no problems with the
bootstrap or tests that regressed. I compared Spec 2017 INT benchmarks and the
number of each instruction matches the previous version I tested. Can I check
this into the GCC trunk?
2019-11-26 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000.md (movdi_internal64): Logically align the
columns of constraints and attributes to make it easier to add new
patterns in the middle. Set the num_insns insn attribute.
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 278747)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -8838,24 +8838,35 @@ (define_split
DONE;
})
-;; GPR store GPR load GPR move GPR li GPR lis GPR #
-;; FPR store FPR load FPR move AVX store AVX store AVX
load
-;; AVX load VSX move P9 0 P9 -1 AVX 0/-1 VSX 0
-;; VSX -1 P9 const AVX const From SPR To SPR
SPR<->SPR
+;; GPR store GPR load GPR move
+;; GPR li GPR lis GPR #
+;; FPR store FPR load FPR move
+;; AVX store AVX store AVX load AVX load VSX move
+;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1
+;; P9 const AVX const
+;; From SPR To SPR SPR<->SPR
;; VSX->GPR GPR->VSX
+
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=YZ, r, r, r, r, r,
- m, ^d, ^d, wY, Z, $v,
- $v, ^wa, wa, wa, v, wa,
- wa, v, v, r, *h, *h,
+ "=YZ, r, r,
+ r, r, r,
+ m, ^d, ^d,
+ wY, Z, $v, $v, ^wa,
+ wa, wa, v, wa, wa,
+ v, v,
+ r, *h, *h,
?r, ?wa")
+
(match_operand:DI 1 "input_operand"
- "r, YZ, r, I, L, nF,
- ^d, m, ^d, ^v, $v, wY,
- Z, ^wa, Oj, wM, OjwM, Oj,
- wM, wS, wB, *h, r, 0,
+ "r, YZ, r,
+ I, L, nF,
+ ^d, m, ^d, ^v, $v,
+ wY, Z, ^wa, Oj, wM,
+ OjwM, Oj, wM, wS, wB,
+ *h, r, 0,
wa, r"))]
+
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -8887,23 +8898,41 @@ (define_insn "*movdi_internal64"
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
- "store, load, *, *, *, *,
- fpstore, fpload, fpsimple, fpstore, fpstore,
fpload,
- fpload, veclogical, vecsimple, vecsimple, vecsimple,
veclogical,
- veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
- mftgpr, mffgpr")
+ "store, load, *,
+ *, *, *,
+ fpstore, fpload, fpsimple,
+ fpstore, fpstore, fpload, fpload, veclogical,
+ vecsimple, vecsimple, vecsimple, veclogical, veclogical,
+ vecsimple, vecsimple,
+ mfjmpr, mtjmpr, *,
+ mftgpr, mffgpr")
(set_attr "size" "64")
(set_attr "length"
- "*, *, *, *, *, 20,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *, 8, *, *, *, *,
- *, *")
+ "*, *, *,
+ *, *, 20,
+ *, *, *,
+ *, *, *, *, *,
+ *, *, *, *, *,
+ 8, *,
+ *, *, *,
+ *, *")
+ (set_attr "num_insns"
+ "*, *, *,
+ *, *, 5,
+ *, *, *,
+ *, *, *, *, *,
+ *, *, *, *, *,
+ 2, *,
+ *, *, *,
+ *, *")
(set_attr "isa"
- "*, *, *, *, *, *,
- *, *, *, p9v, p7v, p9v,
- p7v, *, p9v, p9v, p7v, *,
- *, p7v, p7v, *, *, *,
+ "*, *, *,
+ *, *, *,
+ *, *, *,
+ p9v, p7v, p9v, p7v, *,
+ p9v, p9v, p7v, *, *,
+ p7v, p7v,
+ *, *, *,
p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
