This is the patch removing discrepancy between recog and LRA insn
recognition:
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01842.html
Index: ChangeLog
===================================================================
--- ChangeLog (revision 278451)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2019-11-19 Vladimir Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/90007
+ * recog.c (constrain_operands): Permit hard registers too for
+ memory when LRA is used.
+
2019-11-19 Martin Liska <mli...@suse.cz>
* toplev.c (general_init): Move the call...
Index: recog.c
===================================================================
--- recog.c (revision 278413)
+++ recog.c (working copy)
@@ -2757,10 +2757,9 @@ constrain_operands (int strict, alternat
/* Before reload, accept what reload can turn
into a mem. */
|| (strict < 0 && CONSTANT_P (op))
- /* Before reload, accept a pseudo,
+ /* Before reload, accept a pseudo or hard register,
since LRA can turn it into a mem. */
- || (strict < 0 && targetm.lra_p () && REG_P (op)
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)
+ || (strict < 0 && targetm.lra_p () && REG_P (op))
/* During reload, accept a pseudo */
|| (reload_in_progress && REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))
Index: testsuite/ChangeLog
===================================================================
--- testsuite/ChangeLog (revision 278451)
+++ testsuite/ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2019-11-19 Vladimir Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/90007
+ * gcc.target/i386/pr90007.c: New test.
+
2019-11-15 Andrew Sutton <asut...@lock3software.com>
PR c++/89913
Index: testsuite/gcc.target/i386/pr90007.c
===================================================================
--- testsuite/gcc.target/i386/pr90007.c (nonexistent)
+++ testsuite/gcc.target/i386/pr90007.c (working copy)
@@ -0,0 +1,15 @@
+/* PR rtl-optimization/90007 */
+/* { dg-do compile { target x86_64-*-* } } */
+/* { dg-options "-march=bdver1 -mfpmath=387 -O1 -fschedule-insns -fselective-scheduling" } */
+
+void
+qj (int b9, int r9, int k4, int k0, int e7)
+{
+ (void) b9;
+ (void) r9;
+ (void) k4;
+
+ while (!!k0 == e7 * 1.1)
+ {
+ }
+}
