This patch tests whether using large numeric offsets causes prefixed loads or stores to be generated.
Can I check this patch into the FSF trunk? 2019-11-14 Michael Meissner <meiss...@linux.ibm.com> * gcc/testsuite/gcc.target/powerpc/prefix-large.h: New set of tests to test prefixed addressing on 'future' system with large numeric offsets. * gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-df.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-di.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-si.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c: New test. * gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c: New test. --- /tmp/RMaUEu_prefix-large-dd.c 2019-11-13 17:42:31.960524470 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c 2019-11-13 17:42:31.719522299 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE _Decimal64 + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplfd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */ --- /tmp/ASyj4G_prefix-large-df.c 2019-11-13 17:42:31.968524542 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-df.c 2019-11-13 17:42:31.725522354 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE double + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplfd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */ --- /tmp/uCv6uT_prefix-large-di.c 2019-11-13 17:42:31.975524605 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-di.c 2019-11-13 17:42:31.730522399 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE long + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */ --- /tmp/M6slX5_prefix-large-hi.c 2019-11-13 17:42:31.983524677 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c 2019-11-13 17:42:31.735522443 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE short + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplh[az]\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpsth\M} 2 } } */ --- /tmp/iEQZqi_prefix-large-kf.c 2019-11-13 17:42:31.990524740 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c 2019-11-13 17:42:31.740522489 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE __float128 + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplxv\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */ --- /tmp/01w3Vu_prefix-large-qi.c 2019-11-13 17:42:31.997524803 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c 2019-11-13 17:42:31.745522534 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE signed char + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplbz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstb\M} 2 } } */ --- /tmp/rcmxsH_prefix-large-sd.c 2019-11-13 17:42:32.004524866 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c 2019-11-13 17:42:31.751522588 -0500 @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE _Decimal32 + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mpaddi\M|\mpli|\mpla\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M} 2 } } */ + + --- /tmp/YCLn0T_prefix-large-sf.c 2019-11-13 17:42:32.011524929 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c 2019-11-13 17:42:31.756522633 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE float + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplfs\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */ --- /tmp/vjxBz6_prefix-large-si.c 2019-11-13 17:42:32.018524992 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-si.c 2019-11-13 17:42:31.760522669 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE int + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplw[az]\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */ --- /tmp/sG3baj_prefix-large-udi.c 2019-11-13 17:42:32.025525055 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c 2019-11-13 17:42:31.764522705 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE unsigned long + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */ --- /tmp/a8y8Lv_prefix-large-uhi.c 2019-11-13 17:42:32.032525118 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c 2019-11-13 17:42:31.766522723 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE unsigned short + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplhz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpsth\M} 2 } } */ --- /tmp/CJTxpI_prefix-large-uqi.c 2019-11-13 17:42:32.040525190 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c 2019-11-13 17:42:31.769522750 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE unsigned char + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplbz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstb\M} 2 } } */ --- /tmp/Vkqi4U_prefix-large-usi.c 2019-11-13 17:42:32.046525244 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c 2019-11-13 17:42:31.771522768 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE unsigned int + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplwz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */ --- /tmp/5CcoK7_prefix-large-v2df.c 2019-11-13 17:42:32.053525307 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c 2019-11-13 17:42:31.773522786 -0500 @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests for prefixed instructions testing whether we can generate a prefixed + load/store instruction that has a 34-bit offset. */ + +#define TYPE vector double + +#include "prefix-large.h" + +/* { dg-final { scan-assembler-times {\mplxv\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */ --- /tmp/ROIUrk_prefix-large.h 2019-11-13 17:42:32.061525379 -0500 +++ gcc/testsuite/gcc.target/powerpc/prefix-large.h 2019-11-13 17:42:31.775522804 -0500 @@ -0,0 +1,59 @@ +/* Common tests for prefixed instructions testing whether we can generate a + 34-bit offset using 1 instruction. */ + +typedef signed char schar; +typedef unsigned char uchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; +typedef long double ldouble; +typedef vector double v2df; +typedef vector long v2di; +typedef vector float v4sf; +typedef vector int v4si; + +#ifndef TYPE +#define TYPE ulong +#endif + +#ifndef ITYPE +#define ITYPE TYPE +#endif + +#ifndef OTYPE +#define OTYPE TYPE +#endif + +#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET) +#define DO_ADD 1 +#define DO_VALUE 1 +#define DO_SET 1 +#endif + +#ifndef CONSTANT +#define CONSTANT 0x123450UL +#endif + +#if DO_ADD +void +add (TYPE *p, TYPE a) +{ + p[CONSTANT] += a; +} +#endif + +#if DO_VALUE +OTYPE +value (TYPE *p) +{ + return p[CONSTANT]; +} +#endif + +#if DO_SET +void +set (TYPE *p, ITYPE a) +{ + p[CONSTANT] = a; +} +#endif -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797