This patch allows using load SImode with sign extend to DImode to generate the
PLWA instruction on the 'future' machine if the offset for the load has the
bottom 2 bits being non-zero. The normal LWA instruction is a DS format
instruction, and it needs the bottom 2 bits to be 0.
This patch was originally part of V5 patch #4.
Along with the other patches, I have done bootstraps on a little endian power8
system, and there were no regressions in the test suite. I have built both
Spec 2006 and Spec 2017 with all of these patches installed using -mcpu=future,
and there were no failures. Can I check this into the trunk?
Note, I may have limited email access on October 17th and 18th, 2019.
2019-10-15 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/predicates.md (lwa_operand): If the bottom two
bits of the offset for the memory address are non-zero, use PLWA
if prefixed instructions are available.
Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md (revision 277017)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -932,6 +932,14 @@ (define_predicate "lwa_operand"
return false;
addr = XEXP (inner, 0);
+
+ /* The LWA instruction uses the DS-form instruction format which requires
+ that the bottom two bits of the offset must be 0. The prefixed PLWA does
+ not have this restriction. While the actual load from memory is 32-bits,
+ we pass in DImode here to test for using a DS instruction. */
+ if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
+ return true;
+
if (GET_CODE (addr) == PRE_INC
|| GET_CODE (addr) == PRE_DEC
|| (GET_CODE (addr) == PRE_MODIFY
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
