On Sat, 12 Oct 2019 at 02:52, Ramana Radhakrishnan <ramana....@googlemail.com> wrote: > > On Fri, Oct 11, 2019 at 6:19 PM Wilco Dijkstra <wilco.dijks...@arm.com> wrote: > > > > Hi Ramana, > > > > > Can you see what happens with the Cortex-A8 or Cortex-A9 schedulers to > > > spread the range across some v7-a CPUs as well ? While they aren't that > > > popular today I > > > would suggest you look at them because the defaults for v7-a are still to > > > use the > > > Cortex-A8 scheduler and the Cortex-A9 scheduler might well also get used > > > in places given > > > the availability of hardware. > > > > The results are practically identical to Cortex-A53 and A57 - there is a > > huge codesize win > > across the board on SPEC2006, there isn't a single benchmark that is larger > > (ie. more > > spilling). > > > > > I'd be happy to move this forward if you could show if there is no > > > *increase* in spills > > > for the same range of benchmarks that you are doing for the Cortex-A8 and > > > Cortex-A9 > > > schedulers. > > > > There certainly isn't. I don't think results like these could be any more > > one-sided, it's a > > significant win for every single benchmark, both for codesize and > > performance! > > > > Ok go ahead - please be sensitive to testsuite regressions. >
Hi Wilco, I've noticed that your patch caused a regression: FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments "internal loop alignment added" 1 Christophe when the compiler is configured --with-mode thumb (or forcing -mthumb when running the tests) > Ramana > > > > What isn't clear is whether something has gone horribly wrong in the > > scheduler which > > could be fixed/reverted, but as it is right now I can't see it being useful > > at all. This means > > we should also reevaluate whether pressure scheduling now hurts AArch64 too. > > > > Cheers, > > Wilco
