This patch is the first of 3 patches to the test framework for the prefixed
(and PC-relative) address support. This patch adds some miscellaneous tests.
It also adds new target supports for prefixed addressing and PC-relative
addressing.
With patches #1-11 installed, these tests all pass. Can I install them into
the trunck once pages 1-11 are committed?
2019-10-08 Michael Meissner <meiss...@linux.ibm.com>
* gcc.target/powerpc/paddi-1.c: New test for loading up 34-bit
DImode constants with PADDI.
* gcc.target/powerpc/paddi-2.c: New test for loading up 32-bit
SImode constants with PADDI.
* /gcc.target/powerpc/paddi-3.c: New test for using PADDI to add
34-bit constants.
* gcc.target/powerpc/prefix-odd-memory.c: New test to make sure
prefixed instructions are generated if an offset would not be
legal for the non-prefixed DS/DQ instructions.
* gcc.target/powerpc/prefix-premodify.c: New test to make sure we
do not generate PRE_INC, PRE_DEC, or PRE_MODIFY on prefixed loads
or stores.
* lib/target-supports.exp
(check_effective_target_powerpc_future_ok): Do not require 64-bit
or Linux support before doing the test. Use a 32-bit constant in
PLI.
(check_effective_target_powerpc_prefixed_addr_ok): New effective
target test to see if prefixed memory instructions are supported.
(check_effective_target_powerpc_pcrel_ok): New effective target
test to test whether PC-relative addressing is supported.
(is-effective-target): Add test for the PowerPC 'future' hardware
support.
Index: gcc/testsuite/gcc.target/powerpc/paddi-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/paddi-1.c (revision 276774)
+++ gcc/testsuite/gcc.target/powerpc/paddi-1.c (working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PADDI is generated to add a large constant. */
+unsigned long
+add (unsigned long a)
+{
+ return a + 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpaddi\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/paddi-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/paddi-2.c (revision 276774)
+++ gcc/testsuite/gcc.target/powerpc/paddi-2.c (working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant. */
+unsigned long
+large (void)
+{
+ return 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/paddi-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/paddi-3.c (revision 276774)
+++ gcc/testsuite/gcc.target/powerpc/paddi-3.c (working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant for SImode. */
+void
+large_si (unsigned int *p)
+{
+ *p = 0x12345U;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-odd-memory.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-odd-memory.c (revision
276774)
+++ gcc/testsuite/gcc.target/powerpc/prefix-odd-memory.c (working copy)
@@ -0,0 +1,156 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests whether we can generate a prefixed load/store operation for addresses
+ that don't meet DS/DQ alignment constraints. */
+
+unsigned long
+load_uc_odd (unsigned char *p)
+{
+ return p[1]; /* should generate LBZ. */
+}
+
+long
+load_sc_odd (signed char *p)
+{
+ return p[1]; /* should generate LBZ + EXTSB. */
+}
+
+unsigned long
+load_us_odd (unsigned char *p)
+{
+ return *(unsigned short *)(p + 1); /* should generate LHZ. */
+}
+
+long
+load_ss_odd (unsigned char *p)
+{
+ return *(short *)(p + 1); /* should generate LHA. */
+}
+
+unsigned long
+load_ui_odd (unsigned char *p)
+{
+ return *(unsigned int *)(p + 1); /* should generate LWZ. */
+}
+
+long
+load_si_odd (unsigned char *p)
+{
+ return *(int *)(p + 1); /* should generate PLWA. */
+}
+
+unsigned long
+load_ul_odd (unsigned char *p)
+{
+ return *(unsigned long *)(p + 1); /* should generate PLD. */
+}
+
+long
+load_sl_odd (unsigned char *p)
+{
+ return *(long *)(p + 1); /* should generate PLD. */
+}
+
+float
+load_float_odd (unsigned char *p)
+{
+ return *(float *)(p + 1); /* should generate LFS. */
+}
+
+double
+load_double_odd (unsigned char *p)
+{
+ return *(double *)(p + 1); /* should generate LFD. */
+}
+
+__ieee128
+load_ieee128_odd (unsigned char *p)
+{
+ return *(__ieee128 *)(p + 1); /* should generate PLXV. */
+}
+
+void
+store_uc_odd (unsigned char uc, unsigned char *p)
+{
+ p[1] = uc; /* should generate STB. */
+}
+
+void
+store_sc_odd (signed char sc, signed char *p)
+{
+ p[1] = sc; /* should generate STB. */
+}
+
+void
+store_us_odd (unsigned short us, unsigned char *p)
+{
+ *(unsigned short *)(p + 1) = us; /* should generate STH. */
+}
+
+void
+store_ss_odd (signed short ss, unsigned char *p)
+{
+ *(signed short *)(p + 1) = ss; /* should generate STH. */
+}
+
+void
+store_ui_odd (unsigned int ui, unsigned char *p)
+{
+ *(unsigned int *)(p + 1) = ui; /* should generate STW. */
+}
+
+void
+store_si_odd (signed int si, unsigned char *p)
+{
+ *(signed int *)(p + 1) = si; /* should generate STW. */
+}
+
+void
+store_ul_odd (unsigned long ul, unsigned char *p)
+{
+ *(unsigned long *)(p + 1) = ul; /* should generate PSTD. */
+}
+
+void
+store_sl_odd (signed long sl, unsigned char *p)
+{
+ *(signed long *)(p + 1) = sl; /* should generate PSTD. */
+}
+
+void
+store_float_odd (float f, unsigned char *p)
+{
+ *(float *)(p + 1) = f; /* should generate STF. */
+}
+
+void
+store_double_odd (double d, unsigned char *p)
+{
+ *(double *)(p + 1) = d; /* should generate STD. */
+}
+
+void
+store_ieee128_odd (__ieee128 ieee, unsigned char *p)
+{
+ *(__ieee128 *)(p + 1) = ieee; /* should generate PSTXV. */
+}
+
+/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlbz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlha\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mplwa\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\msth\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-premodify.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-premodify.c (revision 276774)
+++ gcc/testsuite/gcc.target/powerpc/prefix-premodify.c (working copy)
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't try to generate a prefixed form of the load and
+ store with update instructions. */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+ unsigned int field;
+ char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+ *q = (++p)->field;
+ return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+ *q = (--p)->field;
+ return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+ (++p)->field = *q;
+ return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+ (--p)->field = *q;
+ return p;
+}
+
+/* { dg-final { scan-assembler-times {\mpli\M|\mpla\M|\mpaddi\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mp?lwzu\M} } } */
+/* { dg-final { scan-assembler-not {\mp?stwzu\M} } } */
+/* { dg-final { scan-assembler-not {\maddis\M} } } */
+/* { dg-final { scan-assembler-not {\maddi\M} } } */
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp (revision 276759)
+++ gcc/testsuite/lib/target-supports.exp (working copy)
@@ -5307,16 +5307,14 @@ proc check_effective_target_powerpc_p9mo
}
}
-# Return 1 if this is a PowerPC target supporting -mfuture.
-# Limit this to 64-bit linux systems for now until other
-# targets support FUTURE.
+# Return 1 if this is a PowerPC target supporting -mcpu=future.
proc check_effective_target_powerpc_future_ok { } {
- if { ([istarget powerpc64*-*-linux*]) } {
+ if { ([istarget powerpc*-*-*]) } {
return [check_no_compiler_messages powerpc_future_ok object {
int main (void) {
long e;
- asm ("pli %0,%1" : "=r" (e) : "n" (0x12345));
+ asm ("pli %0,%1" : "=r" (e) : "n" (0x1234));
return e;
}
} "-mfuture"]
@@ -5325,6 +5323,46 @@ proc check_effective_target_powerpc_futu
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=future. The compiler
+# must support large numeric prefixed addresses by default when -mfuture is
+# used. We test loading up a large constant to verify that the full 34-bit
+# offset for prefixed instructions is supported and we check for a prefixed
+# load as well.
+
+proc check_effective_target_powerpc_prefixed_addr_ok { } {
+ if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages powerpc_prefixed_addr_ok object {
+ int main (void) {
+ extern long l[];
+ long e, e2;
+ asm ("pli %0,%1" : "=r" (e) : "n" (0x12345678));
+ asm ("pld %0,0x12345678(%1)" : "=r" (e2) : "r" (& l[0]));
+ return e - e2;
+ }
+ } "-mfuture"]
+ } else {
+ return 0
+ }
+}
+
+# Return 1 if this is a PowerPC target supporting -mfuture. The compiler must
+# support PC-relative addressing when -mcpu=future is used to pass this test.
+
+proc check_effective_target_powerpc_pcrel_ok { } {
+ if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages powerpc_pcrel_ok object {
+ int main (void) {
+ static int s __attribute__((__used__));
+ int e;
+ asm ("plwa %0,s@pcrel(0),1" : "=r" (e));
+ return e;
+ }
+ } "-mfuture"]
+ } else {
+ return 0
+ }
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
@@ -7200,6 +7238,7 @@ proc is-effective-target { arg } {
"named_sections" { set selected [check_named_sections_available] }
"gc_sections" { set selected [check_gc_sections_available] }
"cxa_atexit" { set selected [check_cxa_atexit_available] }
+ "powerpc_future_hw" { set selected
[check_powerpc_future_hw_available] }
default { error "unknown effective target keyword `$arg'" }
}
}
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
