On Thu, Sep 5, 2019 at 3:03 PM Segher Boessenkool <seg...@kernel.crashing.org> wrote: > My big question is why do other targets not have this problem? Or what > is it they do differently?
RISC-V doesn't have convenient sign/zero extend instructions. We also have a 12-bit immediate, whereas most other RISCs have a 16-bit immediate, so we can't easily load a constant and mask to zero-extend an HImode value. Thus we have a fair amount of splitters that emit two shifts for zero/sign extend operations, or try to optimize various combinations of shifts or AND operations that can map to instructions that we do have. We also have two splitters that were reusing input registers for intermediate values when they should have been using a clobber to get a temporary. The failure case is when we end up generating something like (lshiftrt:DI (subreg:DI (reg:SI)) (const_int 48)) after a 48 bit left shift with a paradoxical reg input reused for an intermediate result, and the rtl simplifier says that must be zero because an SImode reg doesn't have any valid bits in the upper 32-bits. This is may also be tied into the fact that we have WORD_REGISTER_OPERATIONS defined. Some funny stuff can happen with that defined, and I think most of the other major ports no longer define it. I haven't yet been tempted enough to try to remove that define from the RISC-V port yet, but suspect it will eventually be necessary. I think the WORD_REGISTER_OPERATIONS define is so badly misused by the optimizer nowadays that it isn't worth the trouble anymore. But removing it will be a lot of work to check for performance and code size regressions, so I haven't looked at it yet, and may not for a long while. The other three patterns that were fixed by adding a check for paradoxical regs have no known failure case, and were only fixed for completeness. These are hypothetically necessary changes, and may not in fact be actually necessary, but they appear to be completely harmless so I saw no harm in adding them. In the testing I did, I never saw a paradoxical reg here. But that isn't proof that a paradoxical reg can never occur here. Jim
