Hi,
this fixes two bugs, one is also a wrong-code bug that turned into an ICE due
to the middle-end sanitation (PR 91603/91612). The other is just an assertion
due to expand_expr_real_1 setting byte-aligned mem_attributes of a SSA_NAME
referring to a CONSTANT_P which is actually 16-byte aligned, this happens
after the we handle misaligned stuff, and therefore causes assertions when
that value is used later on, but this is no wrong-code.
Bootstrapped and reg-tested on x86_64-pc-linux-gnu and arm-linux-gnueabihf.
Is it OK for trunk?
Thanks
Bernd.
2019-09-03 Bernd Edlinger <bernd.edlin...@hotmail.de>
PR middle-end/91603
PR middle-end/91612
PR middle-end/91613
* expr.c (expand_expr_real_1): decl_p_1): Refactor into...
(non_mem_decl_p): ...this.
(mem_ref_refers_to_non_mem_p): Handle DECL_P as well ase MEM_REF.
(expand_assignment): Call mem_ref_referes_to_non_mem_p
unconditionally as before.
testsuite:
2019-09-03 Bernd Edlinger <bernd.edlin...@hotmail.de>
PR middle-end/91603
* testsuite/gcc.target/arm/pr91603.c: New test.
Index: gcc/expr.c
===================================================================
--- gcc/expr.c (Revision 275320)
+++ gcc/expr.c (Arbeitskopie)
@@ -10062,7 +10062,43 @@ expand_expr_real_1 (tree exp, rtx target, machine_
{
if (exp && MEM_P (temp) && REG_P (XEXP (temp, 0)))
mark_reg_pointer (XEXP (temp, 0), DECL_ALIGN (exp));
+ }
+ else if (MEM_P (decl_rtl))
+ temp = decl_rtl;
+ if (temp != 0)
+ {
+ if (MEM_P (temp)
+ && modifier != EXPAND_WRITE
+ && modifier != EXPAND_MEMORY
+ && modifier != EXPAND_INITIALIZER
+ && modifier != EXPAND_CONST_ADDRESS
+ && modifier != EXPAND_SUM
+ && !inner_reference_p
+ && mode != BLKmode
+ && MEM_ALIGN (temp) < GET_MODE_ALIGNMENT (mode))
+ {
+ enum insn_code icode;
+
+ if ((icode = optab_handler (movmisalign_optab, mode))
+ != CODE_FOR_nothing)
+ {
+ class expand_operand ops[2];
+
+ /* We've already validated the memory, and we're creating a
+ new pseudo destination. The predicates really can't fail,
+ nor can the generator. */
+ create_output_operand (&ops[0], NULL_RTX, mode);
+ create_fixed_operand (&ops[1], temp);
+ expand_insn (icode, 2, ops);
+ temp = ops[0].value;
+ }
+ else if (targetm.slow_unaligned_access (mode, MEM_ALIGN (temp)))
+ temp = extract_bit_field (temp, GET_MODE_BITSIZE (mode),
+ 0, unsignedp, NULL_RTX,
+ mode, mode, false, NULL);
+ }
+
return temp;
}
@@ -10974,9 +11010,10 @@ expand_expr_real_1 (tree exp, rtx target, machine_
op0 = copy_rtx (op0);
/* Don't set memory attributes if the base expression is
- SSA_NAME that got expanded as a MEM. In that case, we should
- just honor its original memory attributes. */
- if (TREE_CODE (tem) != SSA_NAME || !MEM_P (orig_op0))
+ SSA_NAME that got expanded as a MEM or a CONSTANT. In that case,
+ we should just honor its original memory attributes. */
+ if (!(TREE_CODE (tem) == SSA_NAME
+ && (MEM_P (orig_op0) || CONSTANT_P (orig_op0))))
set_mem_attributes (op0, exp, 0);
if (REG_P (XEXP (op0, 0)))
Index: gcc/testsuite/gcc.target/arm/pr91603.c
===================================================================
--- gcc/testsuite/gcc.target/arm/pr91603.c (Revision 0)
+++ gcc/testsuite/gcc.target/arm/pr91603.c (Arbeitskopie)
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O3" } */
+/* { dg-add-options arm_neon } */
+
+typedef __simd64_int32_t int32x2_t;
+typedef __attribute__((aligned (1))) int32x2_t unalignedvec;
+
+unalignedvec a = {11, 13};
+
+void foo(unalignedvec *);
+
+void test()
+{
+ unalignedvec x = a;
+ foo (&x);
+ a = x;
+}
+
+/* { dg-final { scan-assembler-times "vld1.32" 1 } } */
+/* { dg-final { scan-assembler-times "vst1.32" 1 } } */
+/* { dg-final { scan-assembler-times "vldr" 1 } } */
+/* { dg-final { scan-assembler-times "vstr" 1 } } */
