Hi Paul,
On Sun, Jul 21, 2019 at 04:06:32AM -0500, Paul Clarke wrote:
> @@ -16864,6 +16865,10 @@ return the value of the FPSCR register. Note, ISA
> @code{__builtin_mffsl()} which permits software to read the control and
> non-sticky status bits in the FSPCR without the higher latency associated
> with
> accessing the sticky status bits. The
> +@code{__builtin_mtfsf} takes a constant 8-bit integer field mask and a
> +representation of the new value of the FPSCR and generates the @code{mtfsf}
> +instruction to copy the supplied value into the FPSCR, subject to the field
> +mask, each bit of which represents a nibble of the FPSCR. The
> @code{__builtin_mtfsb0} and @code{__builtin_mtfsb1} take the bit to change
> as an argument. The valid bit range is between 0 and 31. The builtins map
> to
> the @code{mtfsb0} and @code{mtfsb1} instructions which take the argument and
"A representation of the new value"? I guess you want to say that it
sits in an FPR?
Before we document __builtin_mtfsf, maybe we should make it work with
the W and/or L fields first, or at least, decide how we want that?
Segher
