On Sun, Nov 20, 2011 at 6:17 PM, Jiangning Liu <jiangning....@arm.com> wrote:
> Hi,
>
> This patch is to implement a peephole like optimization in ARM back-end.
>
> If we have an if condition expression like "((r3 != 0) & r1) != 0",
So this is the same as:
int f1(int r1, int r3)
{
if (((r3 != 0) & r1) != 0)
return g();
return 1;
}
--- CUT ---
Can't you do this instead:
Combine the following two instructions:
(insn 17 15 18 2 (parallel [
(set (reg:SI 150)
(and:SI (ne:SI (reg:SI 0 r0 [ r1 ])
(const_int 0 [0]))
(reg:SI 1 r1 [ r3 ])))
(clobber (reg:CC 24 cc))
]) t24.c:11 274 {*cond_arith}
(expr_list:REG_UNUSED (reg:CC 24 cc)
(expr_list:REG_DEAD (reg:SI 1 r1 [ r3 ])
(expr_list:REG_DEAD (reg:SI 0 r0 [ r1 ])
(nil)))))
(insn 18 17 19 2 (set (reg:CC 24 cc)
(compare:CC (reg:SI 150)
(const_int 0 [0]))) t24.c:11 211 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 150)
(nil)))
And then have a pattern which expands it to (note the r3 here is the
r3 in the function, likewise for r1):
andi r1, r1, #1
cmp r3, #0
it ne
cmpne r1, #0
Yes it is one extra instruction but it is still better than before right?
