On Mon, Jun 24, 2019 at 03:49:35PM +0800, Kewen.Lin wrote:
> > It sounds like we can have a clean up for some others like
> > TARGET_EXTSWSLI. :)
>
> Sorry, maybe not, it's not similar to maddld for 32bit operations.
Hey, it currently is
(define_insn_and_split "ashdi3_extswsli"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(ashift:DI
(sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "r,m"))
(match_operand:DI 2 "u6bit_cint_operand" "n,n")))]
so you could just do
(define_insn_and_split "ashdi3_extswsli"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(ashift:GPR
(sign_extend:GPR (match_operand:SI 1 "reg_or_mem_operand" "r,m"))
(match_operand:GPR 2 "u6bit_cint_operand" "n,n")))]
and that will work, just generate insn patterns that will never match for SI.
But you can also do
(define_insn_and_split "ashl<mode>3_extswsli"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
(ashift:EXTSI
(sign_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "r,m"))
(match_operand:EXTSI 2 "u6bit_cint_operand" "n,n")))]
and that should work fine, without needing any explicit TARGET_POWERPC64.
But now you need to adjust direct callers of this pattern (which probably
do exist, it is a named pattern (i.e. without *) for a reason ;-)
Segher
