On 6/7/19, H.J. Lu <hjl.to...@gmail.com> wrote:
>> @@ -18702,9 +18705,16 @@
>> if (STACK_REGNO_P (regno))
>> return VALID_FP_MODE_P (mode);
>> if (MASK_REGNO_P (regno))
>> - return (VALID_MASK_REG_MODE (mode)
>> - || (TARGET_AVX512BW
>> - && VALID_MASK_AVX512BW_MODE (mode)));
>> + {
>> + /* Register pair only starts at even register number. */
>> + if ((mode == P2QImode || mode == P2HImode))
>> + return (regno & 1) == 0;
>> +
>> + return (VALID_MASK_REG_MODE (mode)
>> + || (TARGET_AVX512BW
>> + && VALID_MASK_AVX512BW_MODE (mode)));
>> + }
>> +
>> if (SSE_REGNO_P (regno))
>>
>> There is no guarantee that the first regno of the mask register set
>> will be odd number. Please rather spell out appropriate mask
>> registers, following the example of MOD4_SSE_REGNO_P.
>>
>
> We can use
>
> #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
> #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
> #define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0)
Yes this would work.
> BTW,
>
> /* For AVX-5124FMAPS or AVX-5124VNNIW
> allow V64SF and V64SI modes for special regnos. */
> if ((TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW)
> && (mode == V64SFmode || mode == V64SImode)
> && MOD4_SSE_REGNO_P (regno))
> return true;
>
> can be optimized to
>
> /* For AVX-5124FMAPS or AVX-5124VNNIW
> allow V64SF and V64SI modes for special regnos. */
> if ((TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW)
> && (mode == V64SFmode || mode == V64SImode))
> return MOD4_SSE_REGNO_P (regno);
Sure, this would be an obvious patch.
Uros.
