> Subject: Re: [Gcc.amd] [Patch 001] [x86 backend] Define march/mtune for > upcoming AMD Bulldozer procesor. > > > Hello! > > > > > This patch defines -march=bdver1 and -mtune=bdver1 flag for the upcoming > > > AMD Bulldozer processor. > Hi, > it seems that bdver/btver is not mentioned in invoke.texi nor changes.html. > Could you please add documentation? > > Honza
Hi Honza, I have added documentation for bdver1/bdver1 in invoke.texi. is Ok to commit? Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 181283) +++ gcc/doc/invoke.texi (working copy) @@ -12803,6 +12803,15 @@ AMD Family 10h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.) +@item bdver1 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit +instruction set extensions.) +@item btver1 +AMD Family 14h core based CPUs with x86-64 instruction set support. (This +supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit +instruction set extensions.) @item winchip-c6 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction set support.
