On Thu, Mar 28, 2019 at 12:10:06AM +1030, Alan Modra wrote:
> Also, using a register move cost of 2 for for power9 direct moves
> gives these fails, even with the .md file tweaks:
> +FAIL: gcc.target/powerpc/vec-set-char.c scan-assembler-not mtvsrwz
> +FAIL: gcc.target/powerpc/vec-set-char.c scan-assembler vspltisb
> +FAIL: gcc.target/powerpc/vec-set-char.c scan-assembler xxspltib
> +FAIL: gcc.target/powerpc/vec-set-int.c scan-assembler-not mtvsrwz
> +FAIL: gcc.target/powerpc/vec-set-int.c scan-assembler vspltisw
> +FAIL: gcc.target/powerpc/vec-set-short.c scan-assembler-not mtvsrwz
> +FAIL: gcc.target/powerpc/vec-set-short.c scan-assembler vspltish
> +FAIL: gcc.target/powerpc/vec-set-short.c scan-assembler xxspltib
> +FAIL: gcc.target/powerpc/vsx-himode3.c scan-assembler lxsihzx
> +FAIL: gcc.target/powerpc/vsx-qimode3.c scan-assembler lxsibzx
> These can be all be fixed by removing "?"s disparaging vector
> alternatives in movsi_internal1 and mov<mode>_internal.
Like this. Bootstrapped and regression tested powerpc64le-linux.
OK for stage1?
* config/rs6000/rs6000.c (rs6000_register_move_cost): Reduce
power9 direct move cost.
* config/rs6000/rs6000.md (movsi_internal1): Don't disparage
vector alternatives.
(mov<mode>_internal): Likewise, excepting alternative that
will be split.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fbc16c65de4..a9e27b356df 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -35010,7 +35010,7 @@ rs6000_register_move_cost (machine_mode mode,
if (rs6000_tune == PROCESSOR_POWER8)
ret = 4 * hard_regno_nregs (0, mode);
else
- ret = 3 * hard_regno_nregs (0, mode);
+ ret = 2 * hard_regno_nregs (0, mode);
/* SFmode requires a conversion when moving between gprs
and vsx. */
if (mode == SFmode)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d383504c600..2fbab973907 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6832,10 +6832,10 @@ (define_insn "movsi_low"
;; MF%1 MT%0 NOP
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, r, ?wI, ?wH,
- m, ?Z, ?Z, r, r,
- r, ?wIwH, ?wJwK, ?wJwK, ?wu,
- ?wJwK, ?wH, ?wK, ?wIwH, ?r,
+ "=r, r, r, wI, wH,
+ m, Z, Z, r, r,
+ r, wIwH, wJwK, wJwK, wu,
+ wJwK, wH, wK, wIwH, r,
r, *h, *h")
(match_operand:SI 1 "input_operand"
@@ -7106,13 +7106,13 @@ (define_expand "mov<mode>"
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, ?wJwK, m, Z, r,
- ?wJwK, ?wJwK, ?wJwK, ?wK, ?wK, r,
- ?wJwK, r, *c*l, *h")
+ "=r, r, wJwK, m, Z, r,
+ wJwK, wJwK, wJwK, wK, ?wK, r,
+ wJwK, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
"r, m, Z, r, wJwK, i,
- wJwK, O, wM, wB, wS, ?wJwK,
+ wJwK, O, wM, wB, wS, wJwK,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
--
Alan Modra
Australia Development Lab, IBM
