From: Xiong Hu Luo <luo...@linux.ibm.com> This is a backport of r255555, r257253 and r258137 of trunk to gcc-7-branch. The patches were on trunk before GCC 8 forked already. Totally 5 files need mannual resolve due to code changes for r255555. r257253 and r258137 are dependent testcases require vsx support need merge to avoid regression.
The discussion for the patch r255555 that went into trunk is: https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00394.html VSX support for patch r257253 and r258137: https://gcc.gnu.org/ml/gcc-patches/2018-01/msg02391.html https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01506.html gcc/ChangeLog: 2019-01-14 Luo Xiong Hu <luo...@linux.ibm.com> Backport from trunk. Mannually resolve 3 files: * config/rs6000/altivec.h (vec_extract_fp32_from_shorth, vec_extract_fp32_from_shortl): Resolve new #defines. * config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_SLD): Resolve new expensions. * doc/extend.texi: (vec_sld, vec_sll, vec_srl, vec_sro, vec_unpackh, vec_unpackl, test_vsi_packsu_vssi_vssi, vec_packsu, vec_cmpne): Resolve new documentation. 2017-12-11 Carl Love <c...@us.ibm.com> * config/rs6000/altivec.h (vec_extract_fp32_from_shorth, vec_extract_fp32_from_shortl]): Add #defines. * config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion. * config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SLL): Add expansions. * doc/extend.texi: Add documentation for the added builtins. gcc/testsuite/ChangeLog: 2019-01-14 Luo Xiong Hu <luo...@linux.ibm.com> Backport from trunk r255555. Mannually resolve 2 files: * gcc.target/powerpc/builtins-3-p8.c (test_vsi_packs_vusi, test_vsi_packsu-vssi, test_vsi_packsu-vusi, test_vsi_packsu-vsll, test_vsi_packsu-vull, test_vsi_packsu-vsi, test_vsi_packsu-vui): Resolve new cases. * gcc.target/powerpc/builtins-3.c (test_sll_vsc_vsc_vsuc, test_sll_vuc_vuc, test_sll_vsi_vsi_vuc, test_sll_vui_vui_vuc, test_sll_vbll_vull, test_sll_vbll_vbll_vus, test_sll_vp_vp_vuc, test_sll_vssi_vssi_vuc, test_sll_vusi_vusi_vuc, test_slo_vsc_vsc_vsc, test_slo_vuc_vuc_vsc, test_slo_vsi_vsi_vsc, test_slo_vsi_vsi_vuc, test_slo_vui_vui_vsc, test_slo_vui_vui_vuc, test_slo_vp_vp_vsc, test_slo_vp_vp_vuc, test_slo_vssi_vssi_vsc, test_slo_vssi_vssi_vuc, test_slo_vusi_vusi_vsc, test_slo_vusi_vusi_vuc, test_slo_vusi_vusi_vuc, test_slo_vf_vf_vsc, test_slo_vf_vf_vuc, test_cmpb_float): Resolve new cases. 2017-12-11 Carl Love <c...@us.ibm.com> * gcc.target/powerpc/altivec-7.c: Renamed altivec-7.h. * gcc.target/powerpc/altivec-7.h (main): Add testcases for vec_unpackl. Add dg-final tests for the instructions generated. * gcc.target/powerpc/altivec-7-be.c: New file to test on big endian. * gcc.target/powerpc/altivec-7-le.c: New file to test on little endian. * gcc.target/powerpc/altivec-13.c (foo): Add vec_sld, vec_srl, vec_sro testcases. Add dg-final tests for the instructions generated. * gcc.target/powerpc/builtins-3-p8.c (test_vsi_packs_vui, test_vsi_packs_vsi, test_vsi_packs_vssi, test_vsi_packs_vusi, test_vsi_packsu-vssi, test_vsi_packsu-vusi, test_vsi_packsu-vsll, test_vsi_packsu-vull, test_vsi_packsu-vsi, test_vsi_packsu-vui): Add testcases. Add dg-final tests for new instructions. * gcc.target/powerpc/p8vector-builtin-2.c (vbschar_eq, vbchar_eq, vuchar_eq, vbint_eq, vsint_eq, viint_eq, vuint_eq, vbool_eq, vbint_ne, vsint_ne, vuint_ne, vbool_ne, vsign_ne, vuns_ne, vbshort_ne): Add tests. Add dg-final instruction tests. * gcc.target/powerpc/vsx-vector-6.c: Renamed vsx-vector-6.h. * gcc.target/powerpc/vsx-vector-6.h (vec_andc,vec_nmsub, vec_nmadd, vec_or, vec_nor, vec_andc, vec_or, vec_andc, vec_msums): Add tests. Add dg-final tests for the generated instructions. * gcc.target/powerpc/builtins-3.c (test_sll_vsc_vsc_vsuc, test_sll_vuc_vuc, test_sll_vsi_vsi_vuc, test_sll_vui_vui_vuc, test_sll_vbll_vull, test_sll_vbll_vbll_vus, test_sll_vp_vp_vuc, test_sll_vssi_vssi_vuc, test_sll_vusi_vusi_vuc, test_slo_vsc_vsc_vsc, test_slo_vuc_vuc_vsc, test_slo_vsi_vsi_vsc, test_slo_vsi_vsi_vuc, test_slo_vui_vui_vsc, test_slo_vui_vui_vuc, test_slo_vsll_slo_vsll_vsc, test_slo_vsll_slo_vsll_vuc, test_slo_vull_slo_vull_vsc, test_slo_vull_slo_vull_vuc, test_slo_vp_vp_vsc, test_slo_vp_vp_vuc, test_slo_vssi_vssi_vsc, test_slo_vssi_vssi_vuc, test_slo_vusi_vusi_vsc, test_slo_vusi_vusi_vuc, test_slo_vusi_vusi_vuc, test_slo_vf_vf_vsc, test_slo_vf_vf_vuc, test_cmpb_float): Add tests. Backport from trunk r257253: 2018-01-31 Will Schmidt <will_schm...@vnet.ibm.com> * gcc.target/powerpc/altivec-13.c: Remove VSX-requiring built-ins. * gcc.target/powerpc/vsx-13.c: New. Backport from trunk r258137: 2018-03-02 Will Schmidt <will_schm...@vnet.ibm.com> * gcc.target/powerpc/altivec-7-be.c: Remove VSX content, allow 32-bit target. * gcc.target/powerpc/altivec-7.h: Remove VSX content. * gcc.target/powerpc/vsx-7-be.c: New test (VSX content). * gcc.target/powerpc/vsx-7.h: New include (VSX content). * gcc.target/powerpc/altivec-7-le.c: Add vsx-7.h include. --- gcc/config/rs6000/altivec.h | 3 + gcc/config/rs6000/rs6000-builtin.def | 1 + gcc/config/rs6000/rs6000-c.c | 38 +++++ gcc/doc/extend.texi | 48 +++++- gcc/testsuite/gcc.target/powerpc/altivec-13.c | 60 +++++++- gcc/testsuite/gcc.target/powerpc/altivec-7-be.c | 30 ++++ gcc/testsuite/gcc.target/powerpc/altivec-7-le.c | 36 +++++ gcc/testsuite/gcc.target/powerpc/altivec-7.c | 46 ------ gcc/testsuite/gcc.target/powerpc/altivec-7.h | 47 ++++++ gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 81 +++++++++- gcc/testsuite/gcc.target/powerpc/builtins-3.c | 168 ++++++++++++++++++++- .../gcc.target/powerpc/p8vector-builtin-2.c | 83 +++++++++- gcc/testsuite/gcc.target/powerpc/vsx-13.c | 42 ++++++ gcc/testsuite/gcc.target/powerpc/vsx-7-be.c | 50 ++++++ gcc/testsuite/gcc.target/powerpc/vsx-7.h | 18 +++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c | 31 ++++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c | 32 ++++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c | 81 ---------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h | 157 +++++++++++++++++++ 19 files changed, 918 insertions(+), 134 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7-be.c create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7-le.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7.h create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-13.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-7-be.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-7.h create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index e04c3a5..b8df599 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -421,6 +421,9 @@ #define vec_insert_exp __builtin_vec_insert_exp #define vec_test_data_class __builtin_vec_test_data_class +#define vec_extract_fp32_from_shorth __builtin_vec_vextract_fp_from_shorth +#define vec_extract_fp32_from_shortl __builtin_vec_vextract_fp_from_shortl + #define scalar_extract_exp __builtin_vec_scalar_extract_exp #define scalar_extract_sig __builtin_vec_scalar_extract_sig #define scalar_insert_exp __builtin_vec_scalar_insert_exp diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 2cc07c6..cb60144 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1000,6 +1000,7 @@ BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) +BU_ALTIVEC_3 (VSLDOI_2DI, "vsldoi_2di", CONST, altivec_vsldoi_v2di) BU_ALTIVEC_3 (VSLDOI_4SF, "vsldoi_4sf", CONST, altivec_vsldoi_v4sf) BU_ALTIVEC_3 (VSLDOI_2DF, "vsldoi_2df", CONST, altivec_vsldoi_v2df) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index f71f13f..c580ec7 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -910,6 +910,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, @@ -940,6 +942,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, @@ -1185,6 +1189,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2542,6 +2548,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, @@ -2742,6 +2760,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, @@ -2774,6 +2796,15 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, @@ -3445,6 +3476,13 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 94e4849..8f73e70 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -15772,6 +15772,8 @@ vector unsigned char vec_vaddubs (vector unsigned char, vector float vec_and (vector float, vector float); vector float vec_and (vector float, vector bool int); vector float vec_and (vector bool int, vector float); +vector bool long long vec_and (vector bool long long int, + vector bool long long); vector bool int vec_and (vector bool int, vector bool int); vector signed int vec_and (vector bool int, vector signed int); vector signed int vec_and (vector signed int, vector bool int); @@ -16701,6 +16703,13 @@ vector unsigned char vec_sld (vector unsigned char, vector bool char vec_sld (vector bool char, vector bool char, const int); +vector bool long long int vec_sld (vector bool long long int, + vector bool long long int, const int); +vector long long int vec_sld (vector long long int, + vector long long int, const int); +vector unsigned long long int vec_sld (vector unsigned long long int, + vector unsigned long long int, + const int); vector signed int vec_sll (vector signed int, vector unsigned int); @@ -16732,6 +16741,10 @@ vector unsigned short vec_sll (vector unsigned short, vector unsigned short); vector unsigned short vec_sll (vector unsigned short, vector unsigned char); +vector long long int vec_sll (vector long long int, + vector unsigned char); +vector unsigned long long int vec_sll (vector unsigned long long int, + vector unsigned char); vector bool short vec_sll (vector bool short, vector unsigned int); vector bool short vec_sll (vector bool short, vector unsigned short); vector bool short vec_sll (vector bool short, vector unsigned char); @@ -16884,6 +16897,10 @@ vector unsigned short vec_srl (vector unsigned short, vector unsigned short); vector unsigned short vec_srl (vector unsigned short, vector unsigned char); +vector long long int vec_srl (vector long long int, + vector unsigned char); +vector unsigned long long int vec_srl (vector unsigned long long int, + vector unsigned char); vector bool short vec_srl (vector bool short, vector unsigned int); vector bool short vec_srl (vector bool short, vector unsigned short); vector bool short vec_srl (vector bool short, vector unsigned char); @@ -16915,6 +16932,14 @@ vector unsigned short vec_sro (vector unsigned short, vector signed char); vector unsigned short vec_sro (vector unsigned short, vector unsigned char); +vector long long int vec_sro (vector long long int, + vector char); +vector long long int vec_sro (vector long long int, + vector unsigned char); +vector unsigned long long int vec_sro (vector unsigned long long int, + vector char); +vector unsigned long long int vec_sro (vector unsigned long long int, + vector unsigned char); vector pixel vec_sro (vector pixel, vector signed char); vector pixel vec_sro (vector pixel, vector unsigned char); vector signed char vec_sro (vector signed char, vector signed char); @@ -17150,6 +17175,7 @@ vector bool short vec_unpackh (vector bool char); vector signed int vec_unpackh (vector signed short); vector bool int vec_unpackh (vector bool short); vector unsigned int vec_unpackh (vector pixel); +vector double vec_unpackh (vector float); vector bool int vec_vupkhsh (vector bool short); vector signed int vec_vupkhsh (vector signed short); @@ -17164,6 +17190,7 @@ vector bool short vec_unpackl (vector bool char); vector unsigned int vec_unpackl (vector pixel); vector signed int vec_unpackl (vector signed short); vector bool int vec_unpackl (vector bool short); +vector double vec_unpackl (vector float); vector unsigned int vec_vupklpx (vector pixel); @@ -17923,9 +17950,16 @@ vector int vec_packs (vector long long, vector long long); vector unsigned int vec_packs (vector unsigned long long, vector unsigned long long); +vector unsigned char vec_packsu (vector signed short, vector signed short ) +vector unsigned char vec_packsu (vector unsigned short, vector unsigned short ) +vector unsigned short int vec_packsu (vector signed int, vector signed int); +vector unsigned short int vec_packsu (vector unsigned int, + vector unsigned int); vector unsigned int vec_packsu (vector long long, vector long long); vector unsigned int vec_packsu (vector unsigned long long, vector unsigned long long); +vector unsigned int vec_packsu (vector signed long long, + vector signed long long); vector long long vec_rl (vector long long, vector unsigned long long); @@ -18143,9 +18177,21 @@ vector unsigned long long vec_bperm (vector unsigned long long, vector unsigned char); vector bool char vec_cmpne (vector bool char, vector bool char); -vector bool short vec_cmpne (vector bool short, vector bool short); +vector bool char vec_cmpne (vector signed char, vector signed char); +vector bool char vec_cmpne (vector unsigned char, vector unsigned char); vector bool int vec_cmpne (vector bool int, vector bool int); +vector bool int vec_cmpne (vector signed int, vector signed int); +vector bool int vec_cmpne (vector unsigned int, vector unsigned int); vector bool long long vec_cmpne (vector bool long long, vector bool long long); +vector bool long long vec_cmpne (vector signed long long, + vector signed long long); +vector bool long long vec_cmpne (vector unsigned long long, + vector unsigned long long); +vector bool short vec_cmpne (vector bool short, vector bool short); +vector bool short vec_cmpne (vector signed short, vector signed short); +vector bool short vec_cmpne (vector unsigned short, vector unsigned short); +vector bool long long vec_cmpne (vector double, vector double); +vector bool int vec_cmpne (vector float, vector float); vector long long vec_vctz (vector long long); vector unsigned long long vec_vctz (vector unsigned long long); diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c index 22ff951..31ff509 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-13.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c @@ -1,21 +1,77 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-options "-maltivec" } */ + /* Author: Ziemowit Laski <zla...@apple.com> */ /* This test case exercises intrinsic/argument combinations that, while not in the Motorola AltiVec PIM, have nevertheless crept into the AltiVec vernacular over the years. */ +/* Tests requiring VSX support (vector long long and vector double) have + been moved over to vsx-13.c. */ + #include <altivec.h> -void foo (void) +void foo (void) { vector bool int boolVec1 = (vector bool int) vec_splat_u32(3); vector bool short boolVec2 = (vector bool short) vec_splat_u16(3); vector bool char boolVec3 = (vector bool char) vec_splat_u8(3); - + vector signed char vsc1, vsc2, vscz; + vector unsigned char vuc1, vuc2, vucz; + vector signed short int vssi1, vssi2, vssiz; + vector signed int vsi1, vsi2, vsiz; + vector unsigned int vui1, vui2, vuiz; + vector unsigned short int vusi1, vusi2, vusiz; + vector pixel vp1, vp2, vpz; + vector float vf1, vf2, vfz; + boolVec1 = vec_sld( boolVec1, boolVec1, 4 ); boolVec2 = vec_sld( boolVec2, boolVec2, 2 ); boolVec3 = vec_sld( boolVec3, boolVec3, 1 ); + + vscz = vec_sld( vsc1, vsc2, 1 ); + vucz = vec_sld( vuc1, vuc2, 1 ); + vsiz = vec_sld( vsi1, vsi2, 1 ); + vuiz = vec_sld( vui1, vui2, 1 ); + vssiz = vec_sld( vssi1, vssi2, 1 ); + vusiz = vec_sld( vusi1, vusi2, 1 ); + + vfz = vec_sld( vf1, vf2, 1 ); + + vpz = vec_sld( vp1, vp2, 1 ); + + vucz = vec_srl(vuc1, vuc2); + vsiz = vec_srl(vsi1, vuc2); + vuiz = vec_srl(vui1, vuc2); + vpz = vec_srl(vp1, vuc2); + vssiz = vec_srl(vssi1, vuc2); + vusiz = vec_srl(vusi1, vuc2); + + vscz = vec_sro(vsc1, vsc2); + vscz = vec_sro(vsc1, vuc2); + vucz = vec_sro(vuc1, vsc2); + vucz = vec_sro(vuc1, vuc2); + vsiz = vec_sro(vsi1, vsc2); + vsiz = vec_sro(vsi1, vuc2); + vuiz = vec_sro(vui1, vsc2); + vuiz = vec_sro(vui1, vuc2); + vpz = vec_sro(vp1, vsc2); + vpz = vec_sro(vp1, vuc2); + vssiz = vec_sro(vssi1, vsc2); + vssiz = vec_sro(vssi1, vuc2); + vusiz = vec_sro(vusi1, vsc2); + vusiz = vec_sro(vusi1, vuc2); + vfz = vec_sro(vf1, vsc2); + vfz = vec_sro(vf1, vuc2); } + +/* Expected results: + vec_sld vsldoi + vec_srl vsr + vec_sro vsro */ + +/* { dg-final { scan-assembler-times "vsldoi" 11 } } */ +/* { dg-final { scan-assembler-times "vsr " 6 } } */ +/* { dg-final { scan-assembler-times "vsro" 16 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c new file mode 100644 index 0000000..1e690be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Expected results for Big Endian: + vec_packpx vpkpx + vec_ld lxvd2x + vec_lde lvewx + vec_ldl lxvl + vec_lvewx lvewx + vec_unpackh vupklsh + vec_unpackl vupkhsh + vec_andc xxnor + xxland + vec_vxor xxlxor + vec_vmsumubm vmsumubm + vec_vmulesb vmulesb + vec_vmulosb vmulosb +*/ + +/* { dg-final { scan-assembler-times "vpkpx" 2 } } */ +/* { dg-final { scan-assembler-times "vmulesb" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 1 } } */ +/* { dg-final { scan-assembler-times "lvewx" 2 } } */ +/* { dg-final { scan-assembler-times "lvxl" 1 } } */ +/* { dg-final { scan-assembler-times "vupklsh" 1 } } */ +/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */ + +/* Source code for the test in altivec-7.h */ +#include "altivec-7.h" diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c new file mode 100644 index 0000000..6e1c8d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target powerpc64le-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Expected results for Little Endian: + vec_packpx vpkpx + vec_vmulosb vmulesb + vec_ld lxv2x + vec_lde lvewx + vec_ldl lxvl + vec_lvewx lvewx + vec_unpackh vupklsh + vec_unpackl vupkhsh + vec_andc xxnor + xxland + vec_vxor xxlxor + vec_vmsumubm vmsumubm + vec_vmulesb vmulosb + vec_vmulosb vmulesb +*/ + +/* { dg-final { scan-assembler-times "vpkpx" 2 } } */ +/* { dg-final { scan-assembler-times "vmulesb" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 1 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 33 } } */ +/* { dg-final { scan-assembler-times "lvewx" 2 } } */ +/* { dg-final { scan-assembler-times "lvxl" 1 } } */ +/* { dg-final { scan-assembler-times "vupklsh" 1 } } */ +/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 4 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 5 } } */ +/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */ + +/* Source code for the test in altivec-7.h and vsx-7.h. */ +#include "altivec-7.h" +#include "vsx-7.h" diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c deleted file mode 100644 index 30a1ee5..0000000 --- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c +++ /dev/null @@ -1,46 +0,0 @@ -/* Origin: Aldy Hernandez <al...@redhat.com> */ - -/* { dg-do compile { target powerpc*-*-* } } */ -/* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec" } */ - -#include <altivec.h> - -int **intp; -int *var_int; -unsigned int **uintp; -vector pixel *varpixel; -vector signed char *vecchar; -vector signed int *vecint; -vector signed short *vecshort; -vector unsigned char *vecuchar; -vector unsigned int *vecuint; -vector unsigned short *vecushort; -vector float *vecfloat; - -int main () -{ - *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]); - *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]); - *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]); - *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); - *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); - *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); - *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); - *vecint++ = vec_ld(var_int[0], intp[1]); - *vecint++ = vec_lde(var_int[0], intp[1]); - *vecint++ = vec_ldl(var_int[0], intp[1]); - *vecint++ = vec_lvewx(var_int[0], intp[1]); - *vecint++ = vec_unpackh(vecshort[0]); - *vecint++ = vec_unpackl(vecshort[0]); - *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]); - *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]); - *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]); - *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]); - *vecuint++ = vec_ld(var_int[0], uintp[1]); - *vecuint++ = vec_lvx(var_int[0], uintp[1]); - *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); - *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.h b/gcc/testsuite/gcc.target/powerpc/altivec-7.h new file mode 100644 index 0000000..4dedcd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.h @@ -0,0 +1,47 @@ +/* Origin: Aldy Hernandez <al...@redhat.com> */ + +/* This test code is included into altivec-7-be.c and altivec-7-le.c. + The two files have the tests for the number of instructions generated for + LE versus BE. */ + +#include <altivec.h> + +int **intp; +int *var_int; +unsigned int **uintp; +vector pixel *varpixel; +vector signed char *vecchar; +vector signed int *vecint; +vector signed short *vecshort; +vector unsigned char *vecuchar; +vector unsigned int *vecuint; +vector unsigned short *vecushort; +vector float *vecfloat; + +int main () +{ + *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]); + *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); + *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); + *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); + *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]); + *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); + *vecint++ = vec_ld(var_int[0], intp[1]); + *vecint++ = vec_lde(var_int[0], intp[1]); + *vecint++ = vec_ldl(var_int[0], intp[1]); + *vecint++ = vec_lvewx(var_int[0], intp[1]); + *vecint++ = vec_unpackh(vecshort[0]); + *vecint++ = vec_unpackl(vecshort[0]); + *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]); + *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]); + *vecuint++ = vec_ld(var_int[0], uintp[1]); + *vecuint++ = vec_lvx(var_int[0], uintp[1]); + *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); + *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c index 92b8f9a..76291dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c @@ -23,6 +23,34 @@ test_nabs_long_long (vector long long x) return vec_nabs (x); } +vector unsigned char +test_vsi_packs_vusi_vusi (vector unsigned short x, + vector unsigned short y) +{ + return vec_packs (x, y); +} + +vector signed char +test_vsi_packs_vssi_vssi (vector signed short x, + vector signed short y) +{ + return vec_packs (x, y); +} + +vector signed short int +test_vsi_packs_vsi_vsi (vector signed int x, + vector signed int y) +{ + return vec_packs (x, y); +} + +vector unsigned short int +test_vsi_packs_vui_vui (vector unsigned int x, + vector unsigned int y) +{ + return vec_packs (x, y); +} + vector signed int test_vsi_packs_vsll_vsll (vector signed long long x, vector signed long long y) @@ -37,13 +65,57 @@ test_vui_packs_vull_vull (vector unsigned long long x, return vec_packs (x, y); } +vector unsigned char +test_vsi_packsu_vssi_vssi (vector signed short x, + vector signed short y) +{ + return vec_packsu (x, y); +} + +vector unsigned char +test_vsi_packsu_vusi_vusi (vector unsigned short x, + vector unsigned short y) +{ + return vec_packsu (x, y); +} + +vector unsigned int +test_vsi_packsu_vsll_vsll (vector signed long long x, + vector signed long long y) +{ + return vec_packsu (x, y); +} + +vector unsigned int +test_vsi_packsu_vull_vull (vector unsigned long long x, + vector unsigned long long y) +{ + return vec_packsu (x, y); +} + +vector unsigned short int +test_vsi_packsu_vsi_vsi (vector signed int x, + vector signed int y) +{ + return vec_packsu (x, y); +} + +vector unsigned short int +test_vsi_packsu_vui_vui (vector unsigned int x, + vector unsigned int y) +{ + return vec_packsu (x, y); +} + /* Expected test results: test_eq_long_long 1 vcmpequd inst test_pack_float 1 vpkudum inst test_nabs_long_long 1 vspltisw, 1 vsubudm, 1 vminsd test_vsi_packs_vsll_vsll 1 vpksdss - test_vui_packs_vull_vull 1 vpkudus */ + test_vui_packs_vull_vull 1 vpkudus + test_vui_packs_vssi_vssi 1 vpkshss + test_vsi_packsu_vssi_vssi 1 vpkshus */ /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */ /* { dg-final { scan-assembler-times "vpkudum" 1 } } */ @@ -51,4 +123,9 @@ test_vui_packs_vull_vull (vector unsigned long long x, /* { dg-final { scan-assembler-times "vsubudm" 1 } } */ /* { dg-final { scan-assembler-times "vminsd" 1 } } */ /* { dg-final { scan-assembler-times "vpksdss" 1 } } */ -/* { dg-final { scan-assembler-times "vpkudus" 1 } } */ +/* { dg-final { scan-assembler-times "vpkudus" 2 } } */ +/* { dg-final { scan-assembler-times "vpkuhus" 2 } } */ +/* { dg-final { scan-assembler-times "vpkshss" 1 } } */ +/* { dg-final { scan-assembler-times "vpkshus" 1 } } */ +/* { dg-final { scan-assembler-times "vpksdus" 1 } } */ +/* { dg-final { scan-assembler-times "vpkuwus" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c index 01aa862..fd5e62e 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c @@ -59,6 +59,170 @@ test_nabs_double (vector double x) return vec_nabs (x); } +vector signed char +test_sll_vsc_vsc_vsuc (vector signed char x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned char +test_sll_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed int +test_sll_vsi_vsi_vuc (vector signed int x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned int +test_sll_vui_vui_vuc (vector unsigned int x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vuc (vector bool long long x, + vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vull (vector bool long long x, + vector unsigned long long y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vus (vector bool long long x, + vector unsigned short y) +{ + return vec_sll (x, y); +} +vector pixel +test_sll_vp_vp_vuc (vector pixel x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed short int +test_sll_vssi_vssi_vuc (vector signed short x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned short int +test_sll_vusi_vusi_vuc (vector unsigned short x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed char +test_slo_vsc_vsc_vsc (vector signed char x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed char +test_slo_vsc_vsc_vuc (vector signed char x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned char +test_slo_vuc_vuc_vsc (vector unsigned char x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned char +test_slo_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector signed int +test_slo_vsi_vsi_vsc (vector signed int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed int +test_slo_vsi_vsi_vuc (vector signed int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned int +test_slo_vui_vui_vsc (vector unsigned int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned int +test_slo_vui_vui_vuc (vector unsigned int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector pixel +test_slo_vp_vp_vsc (vector pixel int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector pixel +test_slo_vp_vp_vuc (vector pixel int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector signed short int +test_slo_vssi_vssi_vsc (vector signed short int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed short int +test_slo_vssi_vssi_vuc (vector signed short int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned short int +test_slo_vusi_vusi_vsc (vector unsigned short int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned short int +test_slo_vusi_vusi_vuc (vector unsigned short int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector float +test_slo_vf_vf_vsc (vector float x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector float +test_slo_vf_vf_vuc (vector float x, vector unsigned char y) + { + return vec_slo (x, y); + } + +vector int +test_cmpb_float (vector float x, vector float y) +{ + return vec_cmpb (x, y); +} + /* Expected test results: test_eq_char 1 vcmpequb inst @@ -69,7 +233,8 @@ test_nabs_double (vector double x) test_nabs_short 1 vspltisw, 1 vsubuhm, 1 vminsh test_nabs_int 1 vspltisw, 1 vsubuwm, 1 vminsw test_nabs_float 1 xvnabssp - test_nabs_double 1 xvnabsdp */ + test_nabs_double 1 xvnabsdp + test_cmpb_float 1 vcmpbfp */ /* { dg-final { scan-assembler-times "vcmpequb" 1 } } */ /* { dg-final { scan-assembler-times "vcmpequh" 1 } } */ @@ -84,4 +249,5 @@ test_nabs_double (vector double x) /* { dg-final { scan-assembler-times "vspltisw" 3 } } */ /* { dg-final { scan-assembler-times "xvnabssp" 1 } } */ /* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "vcmpbfp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c index 13df148..b572779 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -9,6 +9,14 @@ typedef vector long long v_sign; typedef vector unsigned long long v_uns; typedef vector bool long long v_bool; +typedef vector bool char v_bchar; +typedef vector bool int v_bint; +typedef vector bool short v_bshort; +typedef vector signed int v_sint; +typedef vector unsigned int v_uint; +typedef vector signed char v_schar; +typedef vector unsigned char v_uchar; +typedef vector float v_float; v_sign sign_add_1 (v_sign a, v_sign b) { @@ -191,15 +199,88 @@ v_sign sign_sra_3 (v_sign a, v_uns b) return vec_vsrad (a, b); } +v_bchar vbchar_eq (v_bchar a, v_bchar b) +{ + return vec_cmpeq (a, b); +} + +v_bchar vbschar_eq (v_schar a, v_schar b) +{ + return vec_cmpeq (a, b); +} + +v_bchar vuchar_eq (v_uchar a, v_uchar b) +{ + return vec_cmpeq (a, b); +} + +v_bint vbint_eq (v_bint a, v_bint b) +{ + return vec_cmpeq (a, b); +} + +v_bint vsint_eq (v_sint a, v_sint b) +{ + return vec_cmpeq (a, b); +} + +v_bint vuint_eq (v_uint a, v_uint b) +{ + return vec_cmpeq (a, b); +} + +v_bool vbool_eq (v_bool a, v_bool b) +{ + return vec_cmpeq (a, b); +} + +v_bint vbint_ne (v_bint a, v_bint b) +{ + return vec_cmpne (a, b); +} + +v_bint vsint_ne (v_sint a, v_sint b) +{ + return vec_cmpne (a, b); +} + +v_bint vuint_ne (v_uint a, v_uint b) +{ + return vec_cmpne (a, b); +} + +v_bool vbool_ne (v_bool a, v_bool b) +{ + return vec_cmpne (a, b); +} + +v_bool vsign_ne (v_sign a, v_sign b) +{ + return vec_cmpne (a, b); +} + +v_bool vuns_ne (v_uns a, v_uns b) +{ + return vec_cmpne (a, b); +} + +v_bshort vbshort_ne (v_bshort a, v_bshort b) +{ + return vec_cmpne (a, b); +} + + /* { dg-final { scan-assembler-times "vaddudm" 5 } } */ /* { dg-final { scan-assembler-times "vsubudm" 6 } } */ /* { dg-final { scan-assembler-times "vmaxsd" 4 } } */ /* { dg-final { scan-assembler-times "vminsd" 3 } } */ /* { dg-final { scan-assembler-times "vmaxud" 2 } } */ /* { dg-final { scan-assembler-times "vminud" 2 } } */ -/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */ +/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */ /* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */ /* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */ /* { dg-final { scan-assembler-times "vrld" 3 } } */ /* { dg-final { scan-assembler-times "vsld" 5 } } */ /* { dg-final { scan-assembler-times "vsrad" 3 } } */ +/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */ +/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-13.c b/gcc/testsuite/gcc.target/powerpc/vsx-13.c new file mode 100644 index 0000000..5b4eb68 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-13.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +/* Variations of tests that require VSX support. This is a variation of + the altivec-13.c testcase. */ + +#include <altivec.h> + +void foo (void) +{ + + vector signed char vsc1, vsc2, vscz; + vector unsigned char vuc1, vuc2, vucz; + vector bool long long vubll1, vubll2, vubllz; + vector signed int long long vsill1, vsill2, vsillz; + vector unsigned int long long vuill1, vuill2, vuillz; + vector double vd1, vd2, vdz; + + vubllz = vec_sld( vubll1, vubll2, 1 ); + vsillz = vec_sld( vsill1, vsill2, 1 ); + vuillz = vec_sld( vuill1, vuill2, 1 ); + + vsillz = vec_srl(vsill1, vuc2); + vuillz = vec_srl(vuill1, vuc2); + + vsillz = vec_sro(vsill1, vsc2); + vsillz = vec_sro(vsill1, vuc2); + vuillz = vec_sro(vuill1, vsc2); + vuillz = vec_sro(vuill1, vuc2); + + vdz = vec_sld( vd1, vd2, 1 ); +} + +/* Expected results: + vec_sld vsldoi + vec_srl vsr + vec_sro vsro */ + +/* { dg-final { scan-assembler-times "vsldoi" 4 } } */ +/* { dg-final { scan-assembler-times "vsr " 2 } } */ +/* { dg-final { scan-assembler-times "vsro" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c new file mode 100644 index 0000000..81230a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +/* This is an extension of altivec-7-be.c, with vsx target features included. */ + +/* Expected results for Big Endian: +(from altivec-7.h) + vec_packpx vpkpx + vec_ld lxvd2x or lxv + vec_lde lvewx + vec_ldl lxvl + vec_lvewx lvewx + vec_andc xxnor + xxland + vec_vxor xxlxor + vec_vmsumubm vmsumubm + vec_vmulesb vmulesb + vec_vmulosb vmulosb +(from vsx-7.h) + vec_unpackl vupkhsh + vec_unpackh vupklsh +*/ + +/* { dg-final { scan-assembler-times "vpkpx" 2 } } */ +/* { dg-final { scan-assembler-times "vmulesb" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 1 } } */ + +// For LE platforms P9 and later, we generate the lxv insn instead of lxvd2x. +/* { dg-final { scan-assembler-times {\mlxvd2x\M} 0 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */ +/* { dg-final { scan-assembler-times {\mlxv\M} 36 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */ +// For LE platforms < P9. +/* { dg-final { scan-assembler-times {\mlxvd2x\M} 33 { target { { powerpc64*le-*-* } && { ! p9vector_hw } } } } } */ +// For BE platforms we generate 6 lxvd2x insns. +/* { dg-final { scan-assembler-times {\mlxvd2x\M} 6 { target { { ! powerpc64*le-*-* } && { ! p9vector_hw } } } } } */ + +/* { dg-final { scan-assembler-times "lvewx" 2 } } */ +/* { dg-final { scan-assembler-times "lvxl" 1 } } */ +/* { dg-final { scan-assembler-times "vupklsh" 1 } } */ +/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 0 } } */ +/* { dg-final { scan-assembler-times "xxland" 4 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 5 } } */ +/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */ + +/* Source code for the 'altivec' test in altivec-7.h */ +/* Source code for the 'vsx' required tests in vsx-7.h */ + +#include "altivec-7.h" +#include "vsx-7.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7.h b/gcc/testsuite/gcc.target/powerpc/vsx-7.h new file mode 100644 index 0000000..fe55472 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-7.h @@ -0,0 +1,18 @@ + +/* This test code is included into vsx-7-be.c. + * this is meant to supplement code in altivec-7.h. */ + +#include <altivec.h> + + +vector float *vecfloat; +vector double *vecdouble; + +int main2 () +{ + + *vecdouble++ = vec_unpackl(vecfloat[0]); + *vecdouble++ = vec_unpackh(vecfloat[0]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c new file mode 100644 index 0000000..a33f6d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +/* Expected instruction counts for Big Endian */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c new file mode 100644 index 0000000..b734761 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +/* Expected instruction counts for Little Endian */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ +/* { dg-final { scan-assembler-times "xxlor" 14 } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 9 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c deleted file mode 100644 index f8e644b..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c +++ /dev/null @@ -1,81 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2" } */ - -#include <altivec.h> - -void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, vector unsigned char *p_uc, int *i) -{ - vector double in0 = in[0]; - vector double in1 = in[1]; - vector double in2 = in[2]; - vector long inl = *p_l; - vector bool long inb = *p_b; - vector unsigned char uc = *p_uc; - - *out++ = vec_abs (in0); - *out++ = vec_add (in0, in1); - *out++ = vec_and (in0, in1); - *out++ = vec_and (in0, inb); - *out++ = vec_and (inb, in0); - *out++ = vec_andc (in0, in1); - *out++ = vec_andc (in0, inb); - *out++ = vec_andc (inb, in0); - *out++ = vec_ceil (in0); - *p_b++ = vec_cmpeq (in0, in1); - *p_b++ = vec_cmpgt (in0, in1); - *p_b++ = vec_cmpge (in0, in1); - *p_b++ = vec_cmplt (in0, in1); - *p_b++ = vec_cmple (in0, in1); - *out++ = vec_div (in0, in1); - *out++ = vec_floor (in0); - *out++ = vec_madd (in0, in1, in2); - *out++ = vec_msub (in0, in1, in2); - *out++ = vec_max (in0, in1); - *out++ = vec_min (in0, in1); - *out++ = vec_msub (in0, in1, in2); - *out++ = vec_mul (in0, in1); - *out++ = vec_nearbyint (in0); - *out++ = vec_nmadd (in0, in1, in2); - *out++ = vec_nmsub (in0, in1, in2); - *out++ = vec_nor (in0, in1); - *out++ = vec_or (in0, in1); - *out++ = vec_or (in0, inb); - *out++ = vec_or (inb, in0); - *out++ = vec_perm (in0, in1, uc); - *out++ = vec_rint (in0); - *out++ = vec_sel (in0, in1, inl); - *out++ = vec_sel (in0, in1, inb); - *out++ = vec_sub (in0, in1); - *out++ = vec_sqrt (in0); - *out++ = vec_trunc (in0); - *out++ = vec_xor (in0, in1); - *out++ = vec_xor (in0, inb); - *out++ = vec_xor (inb, in0); - - *i++ = vec_all_eq (in0, in1); - *i++ = vec_all_ge (in0, in1); - *i++ = vec_all_gt (in0, in1); - *i++ = vec_all_le (in0, in1); - *i++ = vec_all_lt (in0, in1); - *i++ = vec_all_nan (in0); - *i++ = vec_all_ne (in0, in1); - *i++ = vec_all_nge (in0, in1); - *i++ = vec_all_ngt (in0, in1); - *i++ = vec_all_nle (in0, in1); - *i++ = vec_all_nlt (in0, in1); - *i++ = vec_all_numeric (in0); - *i++ = vec_any_eq (in0, in1); - *i++ = vec_any_ge (in0, in1); - *i++ = vec_any_gt (in0, in1); - *i++ = vec_any_le (in0, in1); - *i++ = vec_any_lt (in0, in1); - *i++ = vec_any_nan (in0); - *i++ = vec_any_ne (in0, in1); - *i++ = vec_any_nge (in0, in1); - *i++ = vec_any_ngt (in0, in1); - *i++ = vec_any_nle (in0, in1); - *i++ = vec_any_nlt (in0, in1); - *i++ = vec_any_numeric (in0); -} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h new file mode 100644 index 0000000..422f8a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h @@ -0,0 +1,157 @@ +/* This test code is included into vsx-vector-6-be.c and vsx-vector-6-le.c. + The two files have the tests for the number of instructions generated for + LE versus BE. */ + +#include <altivec.h> + +void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, + vector unsigned char *p_uc, int *i, vector float *p_f, + vector bool char *outbc, vector bool int *outbi, + vector bool short *outbsi, vector int *outsi, vector unsigned int *outui) +{ + vector double in0 = in[0]; + vector double in1 = in[1]; + vector double in2 = in[2]; + vector long inl = *p_l; + vector bool long inb = *p_b; + vector bool long long inbl0; + vector bool long long inbl1; + vector unsigned char uc = *p_uc; + vector float inf0; + vector float inf1; + vector float inf2; + vector bool char inbc0; + vector bool char inbc1; + vector bool short inbs0; + vector bool short inbs1; + vector bool int inbi0; + vector bool int inbi1; + vector signed short int inssi0, inssi1; + vector unsigned short int inusi0, inusi1; + vector signed int insi0, insi1; + vector unsigned int inui0, inui1; + + *out++ = vec_abs (in0); + *out++ = vec_add (in0, in1); + *out++ = vec_and (in0, in1); + *out++ = vec_and (in0, inb); + *out++ = vec_and (inb, in0); + *out++ = vec_andc (in0, in1); + *out++ = vec_andc (in0, inb); + *out++ = vec_andc (inb, in0); + *out++ = vec_andc (inbl0, in0); + *out++ = vec_andc (in0, inbl0); + + *out++ = vec_ceil (in0); + *p_b++ = vec_cmpeq (in0, in1); + *p_b++ = vec_cmpgt (in0, in1); + *p_b++ = vec_cmpge (in0, in1); + *p_b++ = vec_cmplt (in0, in1); + *p_b++ = vec_cmple (in0, in1); + *out++ = vec_div (in0, in1); + *out++ = vec_floor (in0); + *out++ = vec_madd (in0, in1, in2); + *out++ = vec_msub (in0, in1, in2); + *out++ = vec_max (in0, in1); + *out++ = vec_min (in0, in1); + *out++ = vec_msub (in0, in1, in2); + *out++ = vec_mul (in0, in1); + *out++ = vec_nearbyint (in0); + *out++ = vec_nmadd (in0, in1, in2); + *out++ = vec_nmsub (in0, in1, in2); + *out++ = vec_nor (in0, in1); + *out++ = vec_or (in0, in1); + *out++ = vec_or (in0, inb); + *out++ = vec_or (inb, in0); + *out++ = vec_perm (in0, in1, uc); + *out++ = vec_rint (in0); + *out++ = vec_sel (in0, in1, inl); + *out++ = vec_sel (in0, in1, inb); + *out++ = vec_sub (in0, in1); + *out++ = vec_sqrt (in0); + *out++ = vec_trunc (in0); + *out++ = vec_xor (in0, in1); + *out++ = vec_xor (in0, inb); + *out++ = vec_xor (inb, in0); + + *i++ = vec_all_eq (in0, in1); + *i++ = vec_all_ge (in0, in1); + *i++ = vec_all_gt (in0, in1); + *i++ = vec_all_le (in0, in1); + *i++ = vec_all_lt (in0, in1); + *i++ = vec_all_nan (in0); + *i++ = vec_all_ne (in0, in1); + *i++ = vec_all_nge (in0, in1); + *i++ = vec_all_ngt (in0, in1); + *i++ = vec_all_nle (in0, in1); + *i++ = vec_all_nlt (in0, in1); + *i++ = vec_all_numeric (in0); + *i++ = vec_any_eq (in0, in1); + *i++ = vec_any_ge (in0, in1); + *i++ = vec_any_gt (in0, in1); + *i++ = vec_any_le (in0, in1); + *i++ = vec_any_lt (in0, in1); + *i++ = vec_any_nan (in0); + *i++ = vec_any_ne (in0, in1); + *i++ = vec_any_nge (in0, in1); + *i++ = vec_any_ngt (in0, in1); + *i++ = vec_any_nle (in0, in1); + *i++ = vec_any_nlt (in0, in1); + *i++ = vec_any_numeric (in0); + + *p_f++ = vec_msub (inf0, inf1, inf2); + *p_f++ = vec_nmsub (inf0, inf1, inf2); + *p_f++ = vec_nmadd (inf0, inf1, inf2); + *p_f++ = vec_or (inf0, inf1); + + *out++ = vec_or (inbl0, in0); + *out++ = vec_or (in0, inbl0); + + *out++ = vec_nor (in0, in1); + + *outbc++ = vec_nor (inbc0, inbc1); + *outbc++ = vec_andc (inbc0, inbc1); + *outbc++ = vec_or (inbc0, inbc1); + + *outbi++ = vec_andc (inbi0, inbi1); + *outbsi++ = vec_andc (inbs0, inbs1); + + *outbsi++ = vec_andc (inbs0, inbs1); + + *outbi++ = vec_nor (inbi0, inbi1); + *outbi++ = vec_or (inbi0, inbi1); + + *outbsi++ = vec_nor (inbs0, inbs1); + *outbsi++ = vec_or (inbs0, inbs1); + + *outsi++ = vec_msums(inssi0, inssi1, insi0); + *outui++ = vec_msums(inusi0, inusi1, inui0); + + *p_f++ = vec_nor (inf0, inf1); + + *p_f++ = vec_andc (inf0, inf1); + *p_f++ = vec_andc (inbi0, inf0); + *p_f++ = vec_andc (inf0, inbi0); + + *in++ = vec_andc (inbl0, in1); + *in++ = vec_andc (in0, inbl1); +} + +int main() +{ + vector double *out; + vector double *in; + vector long *p_l; + vector bool long *p_b; + vector unsigned char *p_uc; + int *i; + vector float *p_f; + vector bool char *outbc; + vector bool int *outbi; + vector bool short *outbsi; + vector int *outsi; + vector unsigned int *outui; + + foo (out, in, p_l, p_b, p_uc, i, p_f, outbc, + outbi, outbsi, outsi, outui); +} -- 2.7.4
