On Wed, Feb 13, 2019 at 2:51 PM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On Wed, Feb 13, 2019 at 9:21 PM H.J. Lu <hjl.to...@gmail.com> wrote:
> >
> > On Tue, Feb 12, 2019 at 4:07 AM Uros Bizjak <ubiz...@gmail.com> wrote:
> > >
> > > On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.to...@gmail.com> wrote:
> > > >
> > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> > > > by default with TARGET_MMX_WITH_SSE.
> > > >
> > > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > > > mode since MMX intrinsics can be emulated wit SSE.
> > > >
> > > > gcc/
> > > >
> > > > PR target/89021
> > > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > > SSE/SSE2/SSSE3.
> > > > * config/i386/i386.c (ix86_option_override_internal): Don't
> > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > (bdesc_tm): Enable MMX intrinsics with SSE/SSE2/SSSE3.
> > > > (ix86_init_mmx_sse_builtins): Likewise.
> > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> > > >
> > > > gcc/testsuite/
> > > >
> > > > PR target/89021
> > > > * gcc.target/i386/pr82483-1.c: Error only on ia32.
> > > > * gcc.target/i386/pr82483-2.c: Likewise.
> > > > ---
> > > > gcc/config/i386/i386-builtin.def | 126 +++++++++++-----------
> > > > gcc/config/i386/i386.c | 62 +++++++----
> > > > gcc/config/i386/mmintrin.h | 10 +-
> > > > gcc/testsuite/gcc.target/i386/pr82483-1.c | 2 +-
> > > > gcc/testsuite/gcc.target/i386/pr82483-2.c | 2 +-
> > > > 5 files changed, 118 insertions(+), 84 deletions(-)
> > > >
> >
> > > > @@ -30810,13 +30815,13 @@ static const struct builtin_description
> > > > bdesc_##kind[] = \
> > > > we're lazy. Add casts to make them fit. */
> > > > static const struct builtin_description bdesc_tm[] =
> > > > {
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN,
> > > > VOID_FTYPE_PV2SI_V2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN,
> > > > VOID_FTYPE_PV2SI_V2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN,
> > > > VOID_FTYPE_PV2SI_V2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN,
> > > > V2SI_FTYPE_PCV2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN,
> > > > V2SI_FTYPE_PCV2SI },
> > > > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64",
> > > > (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN,
> > > > V2SI_FTYPE_PCV2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64,
> > > > UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_WaRM64", (enum ix86_builtins)
> > > > BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_WaWM64", (enum ix86_builtins)
> > > > BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64,
> > > > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64,
> > > > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64,
> > > > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > > > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > > > "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64,
> > > > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > >
> > > Please explain why you need the above change.
> >
> > Reverted.
>
> Actually, I don't know if this change is needed or not, since I don't
> know ITM that good. We still have __m64 (V2SI) loads and stores; they
> are handled by a different (SSE2) instruction, but the access is still
> there. Does ITM care if the access is atomic or not? I don't know.
>
There are no TM testcase for __m64. I have not idea if it works.
--
H.J.
