Hi All,
On AArch64 aarch64_classify_address has a case for when it's non-strict
that will allow it to accept any byte offset from a reg when validating
an address in a given addressing mode.
This because reload would later make the address valid. SVE however requires
the address always be valid, but currently allows any address when a MEM +
offset is used. This causes an ICE as nothing later forces the address to be
legitimate.
The patch forces aarch64_emit_sve_pred_move to ensure that the addressing mode
is valid for any loads/stores it creates, which follows the SVE way of handling
address classifications.
Bootstrapped on aarch64-none-linux-gnu and no issues.
Regtested on aarch64-none-elf with SVE on and no issues.
Ok for trunk?
Thanks,
Tamar
gcc/ChangeLog:
2019-02-11 Tamar Christina <tamar.christ...@arm.com>
PR target/88847
* config/aarch64/aarch64.c (aarch64_classify_address):
For SVE enforce that the address is always valid when doing a MEM +
offset.
gcc/testsuite/ChangeLog:
2019-02-11 Tamar Christina <tamar.christ...@arm.com>
PR target/88847
* gcc.target/aarch64/sve/pr88847.c: New test.
--
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5df5a8b78439e69705e62845a4d1f86166a01894..59f03e688e58c1aab37629555c7b3f19e5075935 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3414,6 +3414,14 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm,
void
aarch64_emit_sve_pred_move (rtx dest, rtx pred, rtx src)
{
+ /* Make sure that the address is legitimate. */
+ if (MEM_P (dest)
+ && !aarch64_sve_struct_memory_operand_p (dest))
+ {
+ rtx addr = force_reg (Pmode, XEXP (dest, 0));
+ dest = replace_equiv_address (dest, addr);
+ }
+
emit_insn (gen_rtx_SET (dest, gen_rtx_UNSPEC (GET_MODE (dest),
gen_rtvec (2, pred, src),
UNSPEC_MERGE_PTRUE)));
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c b/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c
new file mode 100644
index 0000000000000000000000000000000000000000..b7504add9a9f2eedf9421328a87b75b53d492860
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr88847.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-additional-options "-O0 -msve-vector-bits=256 -mbig-endian --save-temps" } */
+
+typedef struct _b {
+ __attribute__((__vector_size__(32))) int a[2];
+} b;
+
+b *c;
+
+void
+foo (void)
+{
+ char *p = '\0';
+ b e = c[0];
+}
+
+/* { dg-final { scan-assembler {\tld1w\tz[0-9]+.s, p[0-9]+/z, \[x[0-9]+\]\n} } } */
+/* { dg-final { scan-assembler {\tld1w\tz[0-9]+.s, p[0-9]+/z, \[x[0-9]+, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tst1w\tz[0-9]+.s, p[0-9]+, \[(sp|x[0-9]+)\]\n} } } */
+/* { dg-final { scan-assembler {\tst1w\tz[0-9]+.s, p[0-9]+, \[(sp|x[0-9]+), #1, mul vl\]\n} } } */
+
