On 2/10/19, H.J. Lu <hjl.to...@gmail.com> wrote:
> Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
> support.
> (*sse2_umulv1siv1di3): Add SSE2 emulation.
OK.
Uros.
> ---
> gcc/config/i386/mmx.md | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index 481b987f4a7..dafc6c4dcb8 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -954,24 +954,30 @@
> (vec_select:V1SI
> (match_operand:V2SI 2 "nonimmediate_operand")
> (parallel [(const_int 0)])))))]
> - "TARGET_SSE2"
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
> "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
>
> (define_insn "*sse2_umulv1siv1di3"
> - [(set (match_operand:V1DI 0 "register_operand" "=y")
> + [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
> (mult:V1DI
> (zero_extend:V1DI
> (vec_select:V1SI
> - (match_operand:V2SI 1 "nonimmediate_operand" "%0")
> + (match_operand:V2SI 1 "nonimmediate_operand" "%0,0,Yv")
> (parallel [(const_int 0)])))
> (zero_extend:V1DI
> (vec_select:V1SI
> - (match_operand:V2SI 2 "nonimmediate_operand" "ym")
> + (match_operand:V2SI 2 "nonimmediate_operand" "ym,x,Yv")
> (parallel [(const_int 0)])))))]
> - "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
> - "pmuludq\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxmul")
> - (set_attr "mode" "DI")])
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> + && TARGET_SSE2
> + && ix86_binary_operator_ok (MULT, V2SImode, operands)"
> + "@
> + pmuludq\t{%2, %0|%0, %2}
> + pmuludq\t{%2, %0|%0, %2}
> + vpmuludq\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxmul,ssemul,ssemul")
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_expand "mmx_<code>v4hi3"
> [(set (match_operand:V4HI 0 "register_operand")
> --
> 2.20.1
>
>
