On Mon, Jan 14, 2019 at 08:02:45AM -0600, wuyuan (E) wrote:
> Hi Kyrill:
> The gcc 7.3.0 does not discard the store1 and load1 command; I did
> not expect the community's latest gcc changes so large .
> now I downloaded the latest GCC code, put the patch into GCC source
> code, the compiler can pass, thank you very much for your work!
>
> Best Regards,
>
> wuyuan
Please check your modeling of Advanced SIMD operations.
> +(define_insn_reservation
> + "tsv110_neon_ld4_lane" 9
> + (and (eq_attr "tune" "tsv110")
> + (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
> + neon_load4_one_lane,neon_load4_one_lane_q"))
> + "((tsv110_ls1*8)|(tsv110_ls2*8)|(tsv110_fsu1*8)|(tsv110_fsu2*8))")
> +
This model says you will reserve
LS1 for 8 cycles,
OR LS2 for 8 cycles,
OR FSU1 for 8 cycles,
OR FSU2 for 8 cycles.
> +(define_insn_reservation "tsv110_neon_abd_aba" 4
> + (and (eq_attr "tune" "tsv110")
> + (eq_attr "type" "neon_abd,neon_arith_acc"))
> + "tsv110_fsu1,tsv110_fsu2")
This model says you will reserve
FSU1 for 1 cycle,
THEN FSU2 for 1 cycle.
> +(define_insn_reservation "tsv110_neon_abd_aba_q" 4
> + (and (eq_attr "tune" "tsv110")
> + (eq_attr "type" "neon_arith_acc_q"))
> + "(tsv110_fsu1,tsv110_fsu2)+(tsv110_fsu1,tsv110_fsu2)")
> +
This model says you will reserve:
FSU1 for 1 cycle,
THEN FSU2 for 1 cycle
AND
FSU1 for 1 cycle,
THEN FSU2 for 1 cycle
Which would be a redundant AND.
Is that how you intend to model these operations?
Remember,
If you are looking to model a 'THEN' relationship you can use the ',' operator,
If you are looking to model an 'AND' relationship you can use the '+' operator,
If you are looking to model an 'OR' relationship you can use the '|' operator.
Taking Cortex-A57 as an example:
> (define_insn_reservation
> "cortex_a57_neon_load_d" 11
> (and (eq_attr "tune" "cortexa57")
> (eq_attr "cortex_a57_neon_type" "neon_load_d"))
> "ca57_cx1_issue+ca57_cx2_issue,
> ca57_ls_issue+ca57_ls_issue,ca57_ldr*2")
This model says you will reserve:
CX1_ISSUE AND CX2_ISSUE,
THEN LS_ISSUE AND LS_ISSUE,
THEN LDR for 2 cycles.
Please let me know if you plan to update the model. If I have misunderstood
your intentions, please accept my apologies.
Best Regards,
James Greenhalgh
>
>
> * config/aarch64/aarch64-cores.def (tsv1100): Change scheduling model.
> * config/aarch64/aarch64.md : Add "tsv110.md"
> * config/aarch64/tsv110.md: New file.
