Hi all,
On 09/01/19 12:26, Richard Sandiford wrote:
Alejandro Martinez Vicente <alejandro.martinezvice...@arm.com> writes:
> Hi,
>
> I updated the patch to address Wilco's comment and style issues.
OK, thanks.
I've committed this on Alejandro's behalf with r267764.
As discussed internally, I think for GCC 10 we should instead make
the vectoriser replace copysign with logic ops if the target has
no better implementation. This would be similar to the existing code
for lowering multiplications by a constant on targets that don't have
general multiplication.
I agree. We should create an enhancement request in bugzilla to track this.
Thanks,
Kyrill
But this optimisation is important for SPEC, and at the moment we have
it for Advanced SIMD and not SVE, which with stretched reasoning you
could call a regression introduced by the SVE port. So the patch seems
OK for GCC 9 as a functionally-correct contingency until we can do
this "properly".
Sorry that this is stretching stage 4 rules a bit. I don't think we
have any other similar patches queued up for GCC 9.
Richard
