Hi James,
> -----Original Message-----
> From: James Greenhalgh <james.greenha...@arm.com>
> Sent: Wednesday, November 28, 2018 17:27
> To: Tamar Christina <tamar.christ...@arm.com>
> Cc: gcc-patches@gcc.gnu.org; nd <n...@arm.com>; Richard Earnshaw
> <richard.earns...@arm.com>; Marcus Shawcroft
> <marcus.shawcr...@arm.com>; ni...@redhat.com; Ramana Radhakrishnan
> <ramana.radhakrish...@arm.com>; Kyrylo Tkachov
> <kyrylo.tkac...@arm.com>
> Subject: Re: [PATCH 5/9][GCC][AArch64/Arm] Add auto-vectorization tests.
>
> On Sun, Nov 11, 2018 at 04:27:33AM -0600, Tamar Christina wrote:
> > Hi All,
> >
> > This patch adds tests for AArch64 and Arm to test the
> > autovectorization of complex numbers using the Armv8.3-a instructions.
> >
> > This patch enables them only for AArch64 at this point.
> >
> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
> >
> > The instructions have also been tested on aarch64-none-elf on a
> > Armv8.3-a model and -march=Armv8.3-a+fp16 and all tests pass.
> >
> > Ok for trunk?
>
> The style seems a bit weird, and there's a whole lot of redundancy I'm not
> keep on. Why have .C files which are always skipped and whose only
> purpose is to be included by another file; don't we normally make them .h
> files to miss the glob in the testsuite?
We do them both ways, but I'll can make these a header since they can't be
tested on their own.
>
> Can we clean up at all?
The only thing I could do is move the input values to the shared files. I
hadn't done this before because it means looking at a testfile you only see
what it's expected values are and not what the input was.
I could of course combine multiple tests into one file, but I find this in
general harder to debug, as you have one test failing out of 40+ and so will
have to go figure out which combination failed first. The abort doesn't tell
you much and prevents further testing.
So I had consciously chosen to have them split, but I can reduce the number of
files using CPP if you prefer.
>
> Some of these have scan-assembler for the Arm backend, which I'm guessing
> is just a rebase issue.
No, since advsimd-intrinsics tests are shared by arm I'd have to either add
skip-if for Arm here or gate the dg-do on AArch64 and in another patch remove
it, so I thought it would be simpler to just combine them.
But I can split them this way if you prefer, the combination is just a
by-product of this sharing between the backends.
Thanks,
Tamar
>
> Thanks,
> James
>
> >
> > Thanks,
> > Tamar
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2018-11-11 Tamar Christina <tamar.christ...@arm.com>
> >
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c: New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c:
> New test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c: New
> test.
> > * gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c: New
> test.
> >
> > --
>
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-aut
> > ovec-270.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-aut
> > ovec-270.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..8f660f392153c3a6a83b31486e
> 27
> > 5be316c6ad2b
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ -autovec-270.c
> > @@ -0,0 +1,13 @@
> > +/* { dg-skip-if "" { *-*-* } } */
> > +
> > +#define N 200
> > +
> > +__attribute__ ((noinline))
> > +void calc (TYPE a[N], TYPE b[N], TYPE *c) {
> > + for (int i=0; i < N; i+=2)
> > + {
> > + c[i] = a[i] + b[i+1];
> > + c[i+1] = a[i+1] - b[i];
> > + }
> > +}
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-aut
> > ovec-90.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-aut
> > ovec-90.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..14014b9d4f2c41e75be3e253d
> 2e4
> > 7e639e4224c0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ -autovec-90.c
> > @@ -0,0 +1,12 @@
> > +/* { dg-skip-if "" { *-*-* } } */
> > +#define N 200
> > +
> > +__attribute__ ((noinline))
> > +void calc (TYPE a[N], TYPE b[N], TYPE *c) {
> > + for (int i=0; i < N; i+=2)
> > + {
> > + c[i] = a[i] - b[i+1];
> > + c[i+1] = a[i+1] + b[i];
> > + }
> > +}
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..627f2e78daee9c4a4f86c20710
> 80
> > b4114820c209
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _1.c
> > @@ -0,0 +1,28 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#include "vcadd-arrays-autovec-90.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != -1.0 || c[1] != 6.0)
> > + abort ();
> > +
> > + if (c[2] != -1.5 || c[3] != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..d94becdb69386c08c07f8b763
> aea
> > 3fa050e6644c
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _2.c
> > @@ -0,0 +1,29 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#include "vcadd-arrays-autovec-90.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != -1.0 || c[1] != 6.0)
> > + abort ();
> > +
> > + if (c[2] != -1.5 || c[3] != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..df33c313847ac2f519deb8346c
> 31
> > 67b015913299
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _3.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#include "vcadd-arrays-autovec-90.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != -1.0 || c[1] != 6.0)
> > + abort ();
> > +
> > + if (c[2] != -1.5 || c[3] != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..bbd4d004177328023eb6270c7
> b38
> > cd9ae0357c60
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _4.c
> > @@ -0,0 +1,29 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#include "vcadd-arrays-autovec-270.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != 3.0 || c[1] != -2.0)
> > + abort ();
> > +
> > + if (c[2] != 7.5 || c[3] != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..8f719d072af591f624f89ef458c
> 0
> > f1552cb38a15
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _5.c
> > @@ -0,0 +1,29 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#include "vcadd-arrays-autovec-270.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != 3.0 || c[1] != -2.0)
> > + abort ();
> > +
> > + if (c[2] != 7.5 || c[3] != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..3f665ba31e2e2debaa7b78f9d
> ce9
> > 07a8f94951e7
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays
> > +++ _6.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#include "vcadd-arrays-autovec-270.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
> > + TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
> > + TYPE c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (c[0] != 3.0 || c[1] != -2.0)
> > + abort ();
> > +
> > + if (c[2] != 7.5 || c[3] != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-au
> > tovec.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-au
> > tovec.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..2a301e6ec0a9ba23a16c39d9c
> 36e
> > e281422f1803
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x-autovec.c
> > @@ -0,0 +1,12 @@
> > +/* { dg-skip-if "" { *-*-* } } */
> > +
> > +#include <complex.h>
> > +
> > +#define N 200
> > +
> > +__attribute__ ((noinline))
> > +void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N]) {
> > + for (int i=0; i < N; i++)
> > + c[i] = a[i] + b[i] ROT;
> > +}
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..a8c596645ccfb60c8994231262
> 0c
> > 31636c3f3f40
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_1.c
> > @@ -0,0 +1,32 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#define ROT * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +#include <stdio.h>
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..abed2b1e824f010feb959d649
> 1df
> > 1b7fcb943d23
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_2.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..e097d79f9867be30b59118578
> b00
> > 540b60fe2b2c
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_3.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..fb4b08bed42452e0a5e9c6315
> a63
> > 17b60c0b5d5d
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_4.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#define ROT * I * I * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..71cc559d1d8c1c9ad0a7a82740
> 24
> > f1954cca04af
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_5.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT * I * I * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..a964b29622b0e2715268c7a03
> a89
> > 4ac48e82e98b
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-comple
> > +++ x_6.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT * I * I * I
> > +#include "vcadd-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {0};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
> > + abort ();
> > +
> > + if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-au
> > tovec.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-au
> > tovec.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..1ad7cc319eeef2ea15f530997a
> 9f
> > fc09571ea02e
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x-autovec.c
> > @@ -0,0 +1,11 @@
> > +/* { dg-skip-if "" { *-*-* } } */
> > +#include <complex.h>
> > +
> > +#define N 200
> > +
> > +__attribute__ ((noinline, noipa))
> > +void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N]) {
> > + for (int i=0; i < N; i++)
> > + c[i] += a[i] * b[i] ROT;
> > +}
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..87a2d25e06fa5ab0b59bc8c9cc
> bf
> > 629f533f0e10
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_1.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +/* { dg-keep-saved-temps ".s" ".o" ".exe" } */ #define TYPE double
> > +#define ROT #include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +#include <stdio.h>
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #(?:0|90)} 2 { target { aarch64*-*-* } } }
> > +} */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_1.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_1.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..8703902944b3e65e2f3dba659
> fc9
> > 425bea4cdd27
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_180_1.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#define ROT * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d,
> > +v[0-9]+\.2d, v[0-9]+\.2d, #(?:180|270)} 2 { target { aarch64*-*-* } }
> > +} } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_2.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_2.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..10833bde24e24d944f2de068f
> 492
> > ac4505b4c012
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_180_2.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #(?:180|270)} 2 { target { aarch64*-*-* } }
> > +} } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_3.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_18
> > 0_3.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..2699577fd7b5a4e565dea702d
> 96e
> > 91e0beded0f2
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_180_3.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #(?:180|270)} 2 { target { aarch64*-*-* } }
> > +} } */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..7bdca9ad5033c99ea7035a7e1
> e0d
> > 411b64db1b73
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_2.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s,
> > +v[0-9]+\.4s, v[0-9]+\.4s, #(?:0|90)} 2 { target { aarch64*-*-* } } }
> > +} */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_1.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_1.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..1c7584d4f949cf448cb1da4219
> f5
> > dd9db14206cb
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_270_1.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#define ROT * I * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_2.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_2.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..eb5cd4ec760031d0ab81d8dcc
> e22
> > 4e94c234c764
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_270_2.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT * I * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_3.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_27
> > 0_3.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..8f1585c14cc0637a17d335b93e
> 91
> > 98b1549f753d
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_270_3.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT * I * I * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.
> > c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.
> > c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..bd8ead4d58884836bbc13005c
> 598
> > 04a26d24617e
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_3.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h,
> > +v[0-9]+\.8h, v[0-9]+\.8h, #(?:0|90)} 2 { target { aarch64*-*-* } } }
> > +} */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _1.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _1.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..fafb8b576b5d3d44ca09c4050b
> e2
> > 20c2195c0eba
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_90_1.c
> > @@ -0,0 +1,33 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_df } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE double
> > +#define ROT * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +#include <stdio.h>
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> > +
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _2.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _2.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..68d395a6075fb19ad79f4f4d41
> db
> > 41bfa4227931
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_90_2.c
> > @@ -0,0 +1,30 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_sf } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -save-temps" } */
> > +
> > +#define TYPE float
> > +#define ROT * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> > diff --git
> > a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _3.c
> > b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90
> > _3.c
> > new file mode 100644
> > index
> >
> 0000000000000000000000000000000000000000..acb566df44e1ce21a7039ae90
> af9
> > bba7c8e49c50
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-comple
> > +++ x_90_3.c
> > @@ -0,0 +1,31 @@
> > +/* { dg-do run } */
> > +/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
> > +/* { dg-require-effective-target vect_complex_rot_hf } */
> > +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
> > +/* { dg-add-options arm_v8_3a_complex_neon } */
> > +/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16
> > +-save-temps" } */
> > +
> > +#define TYPE _Float16
> > +#define ROT * I
> > +#include "vcmla-complex-autovec.c"
> > +
> > +extern void abort(void);
> > +
> > +int main()
> > +{
> > + TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
> > + TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
> > + TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
> > + calc (a, b, c);
> > +
> > + if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
> > + abort ();
> > +
> > + if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
> > + abort ();
> > +
> > + return 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* }
> > +} } } */
> > +/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } }
> > +} */
> >
