Hi,
This patch fixes the FPU configurations of Cortex-R7 and Cortex-R8,
enabling the use of FP16 conversion instructions for both and adding the
option to disable double precision instruction support using '+nofp.dp'.
Passes the self-check during building for an arm target.
Is this OK for trunk?
And could I also backport this to GCC-8?
gcc/ChangeLog:
2018-11-27 Andre Vieira <andre.simoesdiasvie...@arm.com>
* config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
(cortex-r8, cortex-r7): Update default and add new configuration.
From 9878f38a3de6001e8876d21f03adbb7ebf551a79 Mon Sep 17 00:00:00 2001
From: Andre Vieira <andre.simoesdiasvie...@arm.com>
Date: Mon, 26 Nov 2018 16:48:46 +0000
Subject: [PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8
Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have
SP only and SP + DP configurations.
---
gcc/config/arm/arm-cpus.in | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index c71409e5dd9bcad525ed98cefd839bed0fd6f8ee..2fed508a46bc138caaac5d9905d8955e29eb7097 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -476,6 +476,8 @@ begin arch armv7-r
optalias vfpv3xd fp.sp
option fp add VFPv3 FP_DBL
optalias vfpv3-d16 fp
+ option vfpv3xd-fp16 add VFPv3 fp16conv
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
option idiv add adiv
option nofp remove ALL_FP
option noidiv remove adiv
@@ -1086,7 +1088,8 @@ end cpu cortex-r5
begin cpu cortex-r7
cname cortexr7
tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
option nofp remove ALL_FP
costs cortex
vendor 41
@@ -1097,7 +1100,8 @@ begin cpu cortex-r8
cname cortexr8
tune for cortex-r7
tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
option nofp remove ALL_FP
costs cortex
vendor 41
--
1.9.1
