On Sun, Nov 4, 2018 at 7:24 AM H.J. Lu <hjl.to...@gmail.com> wrote:
>
> On Fri, Oct 26, 2018 at 12:44 AM H.J. Lu <hjl.to...@gmail.com> wrote:
> >
> > On 10/25/18, Uros Bizjak <ubiz...@gmail.com> wrote:
> > > On Fri, Oct 26, 2018 at 8:48 AM H.J. Lu <hjl.to...@gmail.com> wrote:
> > >>
> > >> On 10/25/18, Uros Bizjak <ubiz...@gmail.com> wrote:
> > >> > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu <hjl.to...@gmail.com> wrote:
> > >> >>
> > >> >> * read-rtl.c (apply_subst_iterator): Handle
> > >> >> define_insn_and_split.
> > >> >> ---
> > >> >> gcc/read-rtl.c | 6 ++++--
> > >> >> 1 file changed, 4 insertions(+), 2 deletions(-)
> > >> >>
> > >> >> diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
> > >> >> index d698dd4af4d..5957c29671a 100644
> > >> >> --- a/gcc/read-rtl.c
> > >> >> +++ b/gcc/read-rtl.c
> > >> >> @@ -275,9 +275,11 @@ apply_subst_iterator (rtx rt, unsigned int, int
> > >> >> value)
> > >> >> if (value == 1)
> > >> >> return;
> > >> >> gcc_assert (GET_CODE (rt) == DEFINE_INSN
> > >> >> + || GET_CODE (rt) == DEFINE_INSN_AND_SPLIT
> > >> >> || GET_CODE (rt) == DEFINE_EXPAND);
> > >> >
> > >> > Can we also handle DEFINE_SPLIT here?
> > >> >
> > >>
> > >> Yes, we could if there were a usage for it. I am reluctant to add
> > >> something
> > >> I have no use nor test for.
> > >
> > > Just split one define_insn_and_split to define_insn and corresponding
> > > define_split.
> > >
> > > define_insn_and_split is a contraction for for the define_insn and
> > > corresponding define_split, so it looks weird to only handle
> > > define_insn_and-split without handling define_split.
> > >
> >
> > Here is the updated patch to handle define_split. Tested with
> >
> > (define_insn "*sse4_1_<code>v8qiv8hi2<mask_name>_2"
> > [(set (match_operand:V8HI 0 "register_operand")
> > (any_extend:V8HI
> > (vec_select:V8QI
> > (subreg:V16QI
> > (vec_concat:V2DI
> > (match_operand:DI 1 "memory_operand")
> > (const_int 0)) 0)
> > (parallel [(const_int 0) (const_int 1)
> > (const_int 2) (const_int 3)
> > (const_int 4) (const_int 5)
> > (const_int 6) (const_int 7)]))))]
> > "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
> > "#")
> >
> > (define_split
> > [(set (match_operand:V8HI 0 "register_operand")
> > (any_extend:V8HI
> > (vec_select:V8QI
> > (subreg:V16QI
> > (vec_concat:V2DI
> > (match_operand:DI 1 "memory_operand")
> > (const_int 0)) 0)
> > (parallel [(const_int 0) (const_int 1)
> > (const_int 2) (const_int 3)
> > (const_int 4) (const_int 5)
> > (const_int 6) (const_int 7)]))))]
> > "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>
> > && can_create_pseudo_p ()"
> > [(set (match_dup 0)
> > (any_extend:V8HI (match_dup 1)))]
> > {
> > operands[1] = adjust_address_nv (operands[1], V8QImode, 0);
> > })
> >
>
> PING:
>
> https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01665.html
>
> This patch blocks an i386 backend patch.
>
PING.
--
H.J.
