Hi Jakub,
On 13/11/18 09:28, Jakub Jelinek wrote:
Hi!
The following testcase ICEs because the predicate and constraints on one of
the operands of @aarch64_compare_and_swapdi aren't consistent. The RA which
goes according to constraints
(insn 15 13 16 2 (set (reg:DI 104)
(const_int 8589934595 [0x200000003])) "pr87839.c":15:3 47
{*movdi_aarch64}
(expr_list:REG_EQUIV (const_int 8589934595 [0x200000003])
(nil)))
(insn 16 15 21 2 (parallel [
(set (reg:CC 66 cc)
(unspec_volatile:CC [
(const_int 0 [0])
] UNSPECV_ATOMIC_CMPSW))
(set (reg:DI 101)
(mem/v:DI (reg/f:DI 99) [-1 S8 A64]))
(set (mem/v:DI (reg/f:DI 99) [-1 S8 A64])
(unspec_volatile:DI [
(reg:DI 104)
(reg:DI 103)
(const_int 0 [0])
(const_int 32773 [0x8005]) repeated x2
] UNSPECV_ATOMIC_CMPSW))
(clobber (scratch:SI))
]) "pr87839.c":15:3 3532 {aarch64_compare_and_swapdi}
(expr_list:REG_UNUSED (reg:DI 101)
(expr_list:REG_UNUSED (reg:CC 66 cc)
(nil))))
when seeing n constraint puts the 0x200000003 constant directly into the
atomic instruction, but the predicate requires that it is either a register,
or shifted positive or negative 12-bit constant and so it fails to split.
The positive shifted constant apparently has I constraint and negative one
J, and other uses of aarch64_plus_operand that have some constraint use
rIJ (or r):
config/aarch64/aarch64.md: (match_operand:GPI 2 "aarch64_plus_operand" "r,I,J"))
config/aarch64/aarch64.md: (match_operand:SI 2 "aarch64_plus_operand"
"r,I,J"))
config/aarch64/aarch64.md: (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J"))
config/aarch64/aarch64.md: (match_operand:GPI 1 "aarch64_plus_operand" "r"))
config/aarch64/aarch64.md: (match_operand:GPI 1 "aarch64_plus_operand"
"r,I,J")))]
I don't have a setup to easily bootstrap/regtest aarch64-linux ATM, could
somebody please include it in their bootstrap/regtest? Thanks.
2018-11-13 Jakub Jelinek <ja...@redhat.com>
PR target/87839
* config/aarch64/atomics.md (@aarch64_compare_and_swap<mode>): Use
rIJ constraint for aarch64_plus_operand rather than rn.
* gcc.target/aarch64/pr87839.c: New test.
This passes bootstrap and regtesting shows no problems on
aarch64-none-linux-gnu.
The change looks good to me but you'll still need maintainer approval.
Thanks,
Kyrill
--- gcc/config/aarch64/atomics.md.jj 2018-11-01 12:06:43.469963662 +0100
+++ gcc/config/aarch64/atomics.md 2018-11-13 09:59:35.660185116 +0100
@@ -71,7 +71,7 @@ (define_insn_and_split "@aarch64_compare
(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
(set (match_dup 1)
(unspec_volatile:GPI
- [(match_operand:GPI 2 "aarch64_plus_operand" "rn") ;; expect
+ [(match_operand:GPI 2 "aarch64_plus_operand" "rIJ") ;; expect
(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;;
desired
(match_operand:SI 4 "const_int_operand") ;;
is_weak
(match_operand:SI 5 "const_int_operand") ;; mod_s
--- gcc/testsuite/gcc.target/aarch64/pr87839.c.jj 2018-11-13 10:13:44.353309416
+0100
+++ gcc/testsuite/gcc.target/aarch64/pr87839.c 2018-11-13 10:13:05.496944699
+0100
@@ -0,0 +1,29 @@
+/* PR target/87839 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+
+long long b[64];
+void foo (void);
+int bar (void (*) (void));
+void qux (long long *, long long) __attribute__((noreturn));
+void quux (long long *, long long);
+
+void
+baz (void)
+{
+ __sync_val_compare_and_swap (b, 4294967298LL, 78187493520LL);
+ __sync_bool_compare_and_swap (b + 1, 8589934595LL, 21474836489LL);
+ __sync_fetch_and_xor (b, 60129542145LL);
+ quux (b, 42949672967LL);
+ __sync_xor_and_fetch (b + 22, 60129542145LL);
+ quux (b + 23, 42949672967LL);
+ if (bar (baz))
+ __builtin_abort ();
+ foo ();
+ __sync_val_compare_and_swap (b, 4294967298LL, 0);
+ __sync_bool_compare_and_swap (b + 1, 8589934595LL, 78187493520LL);
+ if (__sync_or_and_fetch (b, 21474836489LL) != 21474836489LL)
+ qux (b + 22, 60129542145LL);
+ __atomic_fetch_nand (b + 23, 42949672967LL, __ATOMIC_RELAXED);
+ bar (baz);
+}
Jakub
