On 10/26/2018 01:00 PM, Segher Boessenkool wrote:
> On Thu, Oct 25, 2018 at 02:07:54PM -0500, Paul Clarke wrote:
>> This is a follow-on to earlier commits for adding compatibility
>> implementations of x86 intrinsics for PPC64LE. This is the first of
>> two patches for SSSE3. This patch adds the 32 x86 intrinsics from
>> <tmmintrin.h> ("SSSE3"). (Patch 2/2 adds tests for these intrinsics,
>> and briefly describes the tests performed.)
>> OK for trunk?
>
> I have acked this before; it is still okay. One thing:
OK, there were substantive changes, so wanted to make sure.
>> + In the specific case of X86 SSE2 (__m128i, __m128d) intrinsics,
>> + the PowerPC VMX/VSX ISA is a good match for vector double SIMD
>> + operations. However scalar double operations in vector (XMM)
>> + registers require the POWER8 VSX ISA (2.07) level. Also there are
>> + important differences for data format and placement of double
>> + scalars in the vector register.
>> +
>> + For PowerISA Scalar double is in FPRs (left most 64-bits of the
>> + low 32 VSRs), while X86_64 SSE2 uses the right most 64-bits of
>> + the XMM. These differences require extra steps on POWER to match
>> + the SSE2 scalar double semantics.
>> +
>> + Most SSE2 scalar double intrinsic operations can be performed more
>> + efficiently as C language double scalar operations or optimized to
>> + use vector SIMD operations. We recommend this for new applications.
>> +
>> + Another difference is the format and details of the X86_64 MXSCR vs
>> + the PowerISA FPSCR / VSCR registers. We recommend applications
>> + replace direct access to the MXSCR with the more portable <fenv.h>
>> + Posix APIs. */
>
> I don't know how relevant and/or correct this comment is to this file
> (it looks like you copied it from previous headers?)
Yep, copied without thinking. I'll just remove the whole block you referenced.
Thanks, again!
PC
