On 10/19/18, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Thu, Oct 18, 2018 at 11:44 PM H.J. Lu <hjl.to...@gmail.com> wrote:
>>
>> Many AVX512 vector operations can broadcast from a scalar memory source.
>> This patch enables memory broadcast for FP add operations.
>>
>> gcc/
>>
>> PR target/72782
>> * config/i386/sse.md
>> (*<plusminus_insn><mode>3<mask_name>_bcst_1): New.
>> (*add<mode>3<mask_name>_bcst_2): Likewise.
>>
>> gcc/testsuite/
>>
>> PR target/72782
>> * gcc.target/i386/avx512-binop-1.h: New file.
>> * gcc.target/i386/avx512-binop-2.h: Likewise.
>> * gcc.target/i386/avx512-binop-3.h: Likewise.
>> * gcc.target/i386/avx512-binop-4.h: Likewise.
>> * gcc.target/i386/avx512-binop-5.h: Likewise.
>> * gcc.target/i386/avx512-binop-6.h: Likewise.
>> * gcc.target/i386/avx512f-add-df-zmm-1.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-1.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-2.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-3.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-4.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-5.c: Likewise.
>> * gcc.target/i386/avx512f-add-sf-zmm-6.c: Likewise.
>> * gcc.target/i386/avx512f-sub-df-zmm-1.c: Likewise.
>> * gcc.target/i386/avx512f-sub-sf-zmm-1.c: Likewise.
>> * gcc.target/i386/avx512f-sub-sf-zmm-2.c: Likewise.
>> * gcc.target/i386/avx512f-sub-sf-zmm-3.c: Likewise.
>> * gcc.target/i386/avx512f-sub-sf-zmm-4.c: Likewise.
>> * gcc.target/i386/avx512f-sub-sf-zmm-5.c: Likewise.
>> * gcc.target/i386/avx512vl-add-sf-xmm-1.c: Likewise.
>> * gcc.target/i386/avx512vl-add-sf-ymm-1.c: Likewise.
>> * gcc.target/i386/avx512vl-sub-sf-xmm-1.c: Likewise.
>> * gcc.target/i386/avx512vl-sub-sf-ymm-1.c: Likewise.
>
> Please use "register_operand" when only registers are involved. Please
> change "nonimmediate_operand" to "register_operand" also in your
> previous FMA patch.
I am checking in this patch.
--
H.J.
From 1cf96b0e724ac0f2d533dc1b8cc1589176431535 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.to...@gmail.com>
Date: Fri, 19 Oct 2018 01:48:31 -0700
Subject: [PATCH] i386: Use register_operand in AVX512 FMA with memory
broadcast
Use "register_operand" in AVX512 FMA with memory broadcast when only
registers are allowed.
* config/i386/sse.md
(*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1):
Replace nonimmediate_operand with register_operand.
(*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_2):
Likewise.
(*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_3):
Likewise.
---
gcc/ChangeLog | 10 ++++++++++
gcc/config/i386/sse.md | 12 ++++++------
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 88ec6863128..ca94f822d75 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2018-10-19 H.J. Lu <hongjiu...@intel.com>
+
+ * config/i386/sse.md
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1):
+ Replace nonimmediate_operand with register_operand.
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_2):
+ Likewise.
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_3):
+ Likewise.
+
2018-10-19 Eric Botcazou <ebotca...@adacore.com>
* cfgexpand.c (expand_one_var): Use specific wording in error message
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 71684d63423..06144dc4662 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3749,8 +3749,8 @@
(define_insn "*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1"
[(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
(fma:VF_AVX512
- (match_operand:VF_AVX512 1 "nonimmediate_operand" "0,v")
- (match_operand:VF_AVX512 2 "nonimmediate_operand" "v,0")
+ (match_operand:VF_AVX512 1 "register_operand" "0,v")
+ (match_operand:VF_AVX512 2 "register_operand" "v,0")
(vec_duplicate:VF_AVX512
(match_operand:<ssescalarmode> 3 "memory_operand" "m,m"))))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition>"
@@ -3763,8 +3763,8 @@
(fma:VF_AVX512
(vec_duplicate:VF_AVX512
(match_operand:<ssescalarmode> 1 "memory_operand" "m,m"))
- (match_operand:VF_AVX512 2 "nonimmediate_operand" "0,v")
- (match_operand:VF_AVX512 3 "nonimmediate_operand" "v,0")))]
+ (match_operand:VF_AVX512 2 "register_operand" "0,v")
+ (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{%1<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %1<avx512bcst>}
@@ -3775,10 +3775,10 @@
(define_insn "*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_3"
[(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
(fma:VF_AVX512
- (match_operand:VF_AVX512 1 "nonimmediate_operand" "0,v")
+ (match_operand:VF_AVX512 1 "register_operand" "0,v")
(vec_duplicate:VF_AVX512
(match_operand:<ssescalarmode> 2 "memory_operand" "m,m"))
- (match_operand:VF_AVX512 3 "nonimmediate_operand" "v,0")))]
+ (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{%2<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<avx512bcst>}
--
2.17.2
