Ping. If I don't hear any objections I will consider this patch as
obvious since the only change is to add noinline attributes to the
tests.
Steve Ellcey
sell...@cavium.com
On Wed, 2018-09-26 at 09:21 -0700, Steve Ellcey wrote:
> A patch for PR tree-optimized/71625 caused regressions in the
> gcc.target/aarch64/vclz.c and gcc.target/aarch64/vneg_s.c tests
> because a couple of routines that were not getting inlined before
> started getting inlined. The inlining is not a bug, the
> generated code is now smaller so some functions that were previously
> not being inlined due to being too large are now getting inlined.
> Because we also generate out-of-line code the scan-assembler-times
> checks are failing. Since inlining or not inlining is not the
> point of this test I added the noinline attribute to all the test_*
> functions and this fixed the test regressions.
>
> Tested on aarch64, OK for checkin?
>
> Steve Ellcey
> sell...@cavium.com
>
>
> 2018-09-26 Steve Ellcey <sell...@cavium.com>
>
> PR tree-optimization/71625
> * /gcc.target/aarch64/vclz.c (test_vclz_s8): Add noinline
> attribute.
> (test_vclz_s16): Ditto.
> (test_vclz_s32): Ditto.
> (test_vclzq_s8): Ditto.
> (test_vclzq_s16): Ditto.
> (test_vclzq_s32): Ditto.
> (test_vclz_u8): Ditto.
> (test_vclz_u16): Ditto.
> (test_vclz_u32): Ditto.
> (test_vclzq_u8): Ditto.
> (test_vclzq_u16): Ditto.
> (test_vclzq_u32): Ditto.
> * gcc.target/aarch64/vneg_s.c (test_vneg_s8): Ditto.
> (test_vneg_s16): Ditto.
> (test_vneg_s32): Ditto.
> (test_vneg_s64): Ditto.
> (test_vnegd_s64): Ditto.
> (test_vnegq_s8): Ditto.
> (test_vnegq_s16): Ditto.
> (test_vnegq_s32): Ditto.
> (test_vnegq_s64): Ditto.
>
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/vclz.c
> b/gcc/testsuite/gcc.target/aarch64/vclz.c
> index 60494a8..a36ee44 100644
> --- a/gcc/testsuite/gcc.target/aarch64/vclz.c
> +++ b/gcc/testsuite/gcc.target/aarch64/vclz.c
> @@ -75,7 +75,7 @@ extern void abort (void);
> if (a [i] != b [i])
> \
> return 1;
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_s8 ()
> {
> int i;
> @@ -107,7 +107,7 @@ test_vclz_s8 ()
> /* Double scan-assembler-times to take account of unsigned
> functions. */
> /* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8b, v\[0-
> 9\]+\.8b" 4 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_s16 ()
> {
> int i;
> @@ -138,7 +138,7 @@ test_vclz_s16 ()
> /* Double scan-assembler-times to take account of unsigned
> functions. */
> /* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4h, v\[0-
> 9\]+\.4h" 10} } */
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_s32 ()
> {
> int i;
> @@ -205,7 +205,7 @@ test_vclz_s32 ()
> /* Double scan-assembler-times to take account of unsigned
> functions. */
> /* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.2s, v\[0-
> 9\]+\.2s" 34 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_s8 ()
> {
> int i;
> @@ -226,7 +226,7 @@ test_vclzq_s8 ()
> /* Double scan-assembler-times to take account of unsigned
> functions. */
> /* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.16b, v\[0-
> 9\]+\.16b" 2 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_s16 ()
> {
> int i;
> @@ -262,7 +262,7 @@ test_vclzq_s16 ()
> /* Double scan-assembler-times to take account of unsigned
> functions. */
> /* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8h, v\[0-
> 9\]+\.8h" 6 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_s32 ()
> {
> int i;
> @@ -303,7 +303,7 @@ test_vclzq_s32 ()
>
> /* Unsigned versions. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_u8 ()
> {
> int i;
> @@ -331,7 +331,7 @@ test_vclz_u8 ()
>
> /* ASM scan near test for signed version. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_u16 ()
> {
> int i;
> @@ -361,7 +361,7 @@ test_vclz_u16 ()
>
> /* ASM scan near test for signed version. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclz_u32 ()
> {
> int i;
> @@ -427,7 +427,7 @@ test_vclz_u32 ()
>
> /* ASM scan near test for signed version. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_u8 ()
> {
> int i;
> @@ -448,7 +448,7 @@ test_vclzq_u8 ()
>
> /* ASM scan near test for signed version. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_u16 ()
> {
> int i;
> @@ -485,7 +485,7 @@ test_vclzq_u16 ()
>
> /* ASM scan near test for signed version. */
>
> -int
> +int __attribute__ ((noinline))
> test_vclzq_u32 ()
> {
> int i;
> diff --git a/gcc/testsuite/gcc.target/aarch64/vneg_s.c
> b/gcc/testsuite/gcc.target/aarch64/vneg_s.c
> index e7f20f2..6947526 100644
> --- a/gcc/testsuite/gcc.target/aarch64/vneg_s.c
> +++ b/gcc/testsuite/gcc.target/aarch64/vneg_s.c
> @@ -87,7 +87,7 @@ extern void abort (void);
> force_simd (res); \
> }
>
> -int
> +int __attribute__ ((noinline))
> test_vneg_s8 ()
> {
> int8x8_t a;
> @@ -107,7 +107,7 @@ test_vneg_s8 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-
> 9\]+\.8b" 1 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vneg_s16 ()
> {
> int16x4_t a;
> @@ -127,7 +127,7 @@ test_vneg_s16 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-
> 9\]+\.4h" 2 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vneg_s32 ()
> {
> int32x2_t a;
> @@ -153,7 +153,7 @@ test_vneg_s32 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-
> 9\]+\.2s" 4 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vneg_s64 ()
> {
> int64x1_t a;
> @@ -189,7 +189,7 @@ test_vneg_s64 ()
> return 0;
> }
>
> -int
> +int __attribute__ ((noinline))
> test_vnegd_s64 ()
> {
> int64_t a, b;
> @@ -208,7 +208,7 @@ test_vnegd_s64 ()
>
> /* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 16
> } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vnegq_s8 ()
> {
> int8x16_t a;
> @@ -231,7 +231,7 @@ test_vnegq_s8 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-
> 9\]+\.16b" 1 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vnegq_s16 ()
> {
> int16x8_t a;
> @@ -251,7 +251,7 @@ test_vnegq_s16 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-
> 9\]+\.8h" 1 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vnegq_s32 ()
> {
> int32x4_t a;
> @@ -271,7 +271,7 @@ test_vnegq_s32 ()
>
> /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-
> 9\]+\.4s" 2 } } */
>
> -int
> +int __attribute__ ((noinline))
> test_vnegq_s64 ()
> {
> int64x2_t a;
