... and extend operands to XFmode instead.
2018-09-17 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (truncxf<mode>2_i387_noop_unspec): Change
operand 0 predicate to nonimmediate operand.
(rint<mode>2_frndint): Remove insn pattern.
(rint<mode>2): Change operand 1 predicate to general_operand.
Extend operand 1 to XFmode and generate rintxf2 insn.
(frndintxf2_<rounding>): Rename from frndint<mode>2_<rounding>.
Do not use X87MODEF mode macro.
(frndintxf2_<rounding>_i387): Rename from
frndint<mode>2_<rounding>_i387. Do not use X87MODEF mode macro.
(<rounding_insn><mode>2): For non-SSE modes, extend operand 1
to XFmode and generate significandxf3 insn.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 264319)
+++ config/i386/i386.md (working copy)
@@ -15093,7 +15093,7 @@
;; all fancy i386 XFmode math functions.
(define_insn "truncxf<mode>2_i387_noop_unspec"
- [(set (match_operand:MODEF 0 "register_operand" "=f")
+ [(set (match_operand:MODEF 0 "nonimmediate_operand" "=mf")
(unspec:MODEF [(match_operand:XF 1 "register_operand" "f")]
UNSPEC_TRUNC_NOOP))]
"TARGET_USE_FANCY_MATH_387"
@@ -16109,22 +16109,10 @@
(set_attr "znver1_decode" "vector")
(set_attr "mode" "XF")])
-(define_insn "rint<mode>2_frndint"
- [(set (match_operand:MODEF 0 "register_operand" "=f")
- (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "0")]
- UNSPEC_FRNDINT))]
- "TARGET_USE_FANCY_MATH_387"
- "frndint"
- [(set_attr "type" "fpspc")
- (set_attr "znver1_decode" "vector")
- (set_attr "mode" "<MODE>")])
-
(define_expand "rint<mode>2"
[(use (match_operand:MODEF 0 "register_operand"))
- (use (match_operand:MODEF 1 "register_operand"))]
- "(TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387))
+ (use (match_operand:MODEF 1 "nonimmediate_operand"))]
+ "TARGET_USE_FANCY_MATH_387
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -16136,7 +16124,14 @@
ix86_expand_rint (operands[0], operands[1]);
}
else
- emit_insn (gen_rint<mode>2_frndint (operands[0], operands[1]));
+ {
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_rintxf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ }
DONE;
})
@@ -16254,9 +16249,9 @@
(UNSPEC_FIST_CEIL "CEIL")])
;; Rounding mode control word calculation could clobber FLAGS_REG.
-(define_insn_and_split "frndint<mode>2_<rounding>"
- [(set (match_operand:X87MODEF 0 "register_operand")
- (unspec:X87MODEF [(match_operand:X87MODEF 1 "register_operand")]
+(define_insn_and_split "frndintxf2_<rounding>"
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
FRNDINT_ROUNDING))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
@@ -16271,18 +16266,18 @@
operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>);
- emit_insn (gen_frndint<mode>2_<rounding>_i387 (operands[0], operands[1],
- operands[2], operands[3]));
+ emit_insn (gen_frndintxf2_<rounding>_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
}
[(set_attr "type" "frndint")
(set_attr "i387_cw" "<rounding>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "XF")])
-(define_insn "frndint<mode>2_<rounding>_i387"
- [(set (match_operand:X87MODEF 0 "register_operand" "=f")
- (unspec:X87MODEF [(match_operand:X87MODEF 1 "register_operand" "0")]
- FRNDINT_ROUNDING))
+(define_insn "frndintxf2_<rounding>_i387"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ FRNDINT_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
"TARGET_USE_FANCY_MATH_387
@@ -16290,7 +16285,7 @@
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
(set_attr "i387_cw" "<rounding>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "XF")])
(define_expand "<rounding_insn>xf2"
[(parallel [(set (match_operand:XF 0 "register_operand")
@@ -16310,11 +16305,11 @@
|| TARGET_MIX_SSE_I387)
&& (flag_fp_int_builtin_inexact || !flag_trapping_math))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && (TARGET_SSE4_1 || !flag_trapping_math
- || flag_fp_int_builtin_inexact))"
+ && (TARGET_SSE4_1 || flag_fp_int_builtin_inexact
+ || !flag_trapping_math))"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && (TARGET_SSE4_1 || !flag_trapping_math || flag_fp_int_builtin_inexact))
+ && (TARGET_SSE4_1 || flag_fp_int_builtin_inexact || !flag_trapping_math))
{
if (TARGET_SSE4_1)
emit_insn (gen_sse4_1_round<mode>2
@@ -16344,7 +16339,14 @@
}
}
else
- emit_insn (gen_frndint<mode>2_<rounding> (operands[0], operands[1]));
+ {
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_<rounding> (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ }
DONE;
})
@@ -16408,7 +16410,6 @@
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_mask_pm (op0, op1));
-
emit_insn (gen_truncxf<mode>2 (operands[0], op0));
DONE;
})
