On 11/01/2011 11:57 AM, Richard Henderson wrote:
Any comments on the expectation, or implementation of signal-fence below?
Should I make the distinction between the memory models here at all?
I think the expectation is that signal_fence is identical to
thread_fence, except the compiler doesn't actually issue the hardware
fence instruction. Just the barrier-ness to the compiler as well as any
data dependencies the memory order imposes needs to be maintained.
Since we don't have any directional barriers yet, I guess anything other
than RELAXED needs to be a full barrier to the compiler. someday when I
have been energetic, we may get directional barriers and then we'll do
something different.
Thats my understanding anyway
At minimum there's another typo in the ifdef section; we really need to
minimize those...
And good job at that! :-) These are paths that have not been tested
until someone implements the rtl patterns... so any typo's would need
to have been caught in the patch review :-) I never claimed to
understand the intricacies of RTL pattern machinery that well...
Andrew
