On Tue, 2018-09-04 at 17:20 +0000, Wilco Dijkstra wrote:
> External Email
>
> Hi Steve,
>
> The latest version compiles the examples I used correctly, so it looks fine
> from that perspective (but see comments below). However the key point of
> the ABI is to enable better code generation when calling a vector function,
> and that will likely require further changes that may conflict with this
> patch.
> Do you have patches for that work outstanding? It seems best to do this in
> one go.
>
> Also did you check there is no regression in code generation for non-vector
> functions?
Yes, I checked for regressions in non-vector functions. They way this
is written, there should be zero changes to any generated code that
does not involve vector functions.
I have some changes to improve code generation for SIMD functions but
it is not ready to go yet. The main change I made to improve code
generation is to modify TARGET_HARD_REGNO_CALL_PART_CLOBBERED to accept
an instruction pointer so we could check to see if the call being made
is to a 'normal' function or a 'simd' function and return the correct
value. Unfortunately, there are many places where we don't have the
call insn available and have to make the pessimistic guess.
I also changed get_call_reg_set_usage so that it could return different
default sets of what registers changed based on whether or not the
function being called was normal or simd. Again, there are some places
where we have to make a pessimistic guess.
>
>
> +/* Return 1 if the register is used by the epilogue. We need to say the
> + return register is used, but only after epilogue generation is complete.
> + Note that in the case of sibcalls, the values "used by the epilogue" are
> + considered live at the start of the called function.
> +
> + For SIMD functions we need to return 1 for FP registers that are saved and
> + restored by a function but not zero in call_used_regs. If we do not do
> + this optimizations may remove the restore of the register. */
> +
> +int
> +aarch64_epilogue_uses (int regno)
> +{
> + if (epilogue_completed && (regno) == LR_REGNUM)
> + return 1;
> + if (aarch64_simd_decl_p (cfun->decl) && FP_SIMD_SAVED_REGNUM_P
> (regno))
> + return 1;
> + return 0;
> +}
>
> I'm not convinced this is a good idea. It suggests GCC doesn't have the
> correct set
> of caller/callee-save registers for vector functions (I don't see a change to
> update
> CALL_USED_REGISTERS or aarch64_hard_regno_call_part_clobbered), which could
> lead to all kinds of interesting issues.
The problem is that there is no single correct set of caller/callee-
saved registers anymore. There is one set for normal functions and a
different set for simd functions. GCC isn't set up to have two
different caller/callee saved ABIs on one target, there is only
one CALL_USED_REGISTERS macro used to set one call_used_regs
array. Should V16-V23 be set in CALL_USED_REGISTERS? For 'normal'
functions, yes. For SIMD functions, no.
>
> +/* Return false for non-leaf SIMD functions in order to avoid
> + shrink-wrapping them. Doing this will lose the necessary
> + save/restore of FP registers. */
> +
> +bool
> +aarch64_use_simple_return_insn_p (void)
> +{
> + if (aarch64_simd_decl_p (cfun->decl) && !crtl->is_leaf)
> + return false;
> +
> + return true;
> +}
>
> Such as this...
>
> Wilco
