Umesh Kalappa wrote:
> Any more suggestions or comments on the patch ?
The patch is suboptimal as it introduces 2 additional instructions in a
fairly common path for a branch that is very unlikely to be taken in
practice.
I'm therefore proposing this alternative patch to fix the issue in an
optimal way. I'm also using this opportunity to update my email address
as the one currently in those files has been obsolete for more than 10
years at this point, in the hope that I get notified of similar issues
directly in the future.
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index c13bf4cb2f6..c19d05c8a2e 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-07-26 Nicolas Pitre <n...@fluxnic.net>
+
+ * config/arm/ieee754-df.S: Don't shortcut denormal handling when
+ exponent goes negative. Update my email address.
+ * config/arm/ieee754-sf.S: Likewise.
+
2018-07-05 James Clarke <jrt...@jrtc27.com>
* configure: Regenerated.
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index 8741aa99245..ee7a9835394 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -1,7 +1,7 @@
/* ieee754-df.S double-precision floating point support for ARM
Copyright (C) 2003-2018 Free Software Foundation, Inc.
- Contributed by Nicolas Pitre (n...@cam.org)
+ Contributed by Nicolas Pitre (n...@fluxnic.net)
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
@@ -238,9 +238,10 @@ LSYM(Lad_a):
movs ip, ip, lsl #1
adcs xl, xl, xl
adc xh, xh, xh
- tst xh, #0x00100000
- sub r4, r4, #1
- bne LSYM(Lad_e)
+ subs r4, r4, #1
+ do_it hs
+ tsths xh, #0x00100000
+ bhi LSYM(Lad_e)
@ No rounding necessary since ip will always be 0 at this point.
LSYM(Lad_l):
diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S
index d80d5e9080c..640c97ed550 100644
--- a/libgcc/config/arm/ieee754-sf.S
+++ b/libgcc/config/arm/ieee754-sf.S
@@ -1,7 +1,7 @@
/* ieee754-sf.S single-precision floating point support for ARM
Copyright (C) 2003-2018 Free Software Foundation, Inc.
- Contributed by Nicolas Pitre (n...@cam.org)
+ Contributed by Nicolas Pitre (n...@fluxnic.net)
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
@@ -168,9 +168,10 @@ LSYM(Lad_e):
LSYM(Lad_a):
movs r1, r1, lsl #1
adc r0, r0, r0
- tst r0, #0x00800000
- sub r2, r2, #1
- bne LSYM(Lad_e)
+ subs r2, r2, #1
+ do_it hs
+ tsths r0, #0x00800000
+ bhi LSYM(Lad_e)
@ No rounding necessary since r1 will always be 0 at this point.
LSYM(Lad_l):
