Hello!
These pattern names are misleading, implying that these are "logical
shift left" and "arithmetic shift left". They are not, they are "shift
logical" and "shift arithmetic". Attached (trivial) patch renames
these patterns to the insn mnemonic they generate.
2011-10-29 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (xop_sha<mode>3): Rename from xop_ashl<mode>3.
Update all uses.
(xop_shl<mode>3): Rename from xop_lshl<mode>3. Update all uses.
* config/i386/i386.c: Update all uses.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline.
Uros.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 180657)
+++ config/i386/sse.md (working copy)
@@ -11253,7 +11253,7 @@
{
rtx neg = gen_reg_rtx (<MODE>mode);
emit_insn (gen_neg<mode>2 (neg, operands[2]));
- emit_insn (gen_xop_lshl<mode>3 (operands[0], operands[1], neg));
+ emit_insn (gen_xop_shl<mode>3 (operands[0], operands[1], neg));
DONE;
})
@@ -11268,7 +11268,7 @@
{
rtx neg = gen_reg_rtx (<MODE>mode);
emit_insn (gen_neg<mode>2 (neg, operands[2]));
- emit_insn (gen_xop_lshl<mode>3 (operands[0], operands[1], neg));
+ emit_insn (gen_xop_shl<mode>3 (operands[0], operands[1], neg));
DONE;
}
})
@@ -11289,7 +11289,7 @@
{
rtx neg = gen_reg_rtx (<MODE>mode);
emit_insn (gen_neg<mode>2 (neg, operands[2]));
- emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], neg));
+ emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], neg));
DONE;
})
@@ -11303,7 +11303,7 @@
{
rtx neg = gen_reg_rtx (V4SImode);
emit_insn (gen_negv4si2 (neg, operands[2]));
- emit_insn (gen_xop_ashlv4si3 (operands[0], operands[1], neg));
+ emit_insn (gen_xop_shav4si3 (operands[0], operands[1], neg));
DONE;
}
})
@@ -11321,7 +11321,7 @@
(match_operand:VI12_128 2 "nonimmediate_operand" "")))]
"TARGET_XOP"
{
- emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
DONE;
})
@@ -11335,7 +11335,7 @@
if (!TARGET_AVX2)
{
operands[2] = force_reg (<MODE>mode, operands[2]);
- emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
DONE;
}
})
@@ -11347,7 +11347,7 @@
(match_operand:VI48_256 2 "nonimmediate_operand" "")))]
"TARGET_AVX2")
-(define_insn "xop_ashl<mode>3"
+(define_insn "xop_sha<mode>3"
[(set (match_operand:VI_128 0 "register_operand" "=x,x")
(if_then_else:VI_128
(ge:VI_128
@@ -11366,7 +11366,7 @@
(set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
-(define_insn "xop_lshl<mode>3"
+(define_insn "xop_shl<mode>3"
[(set (match_operand:VI_128 0 "register_operand" "=x,x")
(if_then_else:VI_128
(ge:VI_128
@@ -11402,7 +11402,7 @@
XVECEXP (par, 0, i) = operands[2];
emit_insn (gen_vec_initv16qi (reg, par));
- emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
+ emit_insn (gen_xop_shav16qi3 (operands[0], operands[1], reg));
DONE;
})
@@ -11434,9 +11434,9 @@
emit_insn (gen_negv16qi2 (reg, reg));
if (<CODE> == LSHIFTRT)
- shift_insn = gen_xop_lshlv16qi3;
+ shift_insn = gen_xop_shlv16qi3;
else
- shift_insn = gen_xop_ashlv16qi3;
+ shift_insn = gen_xop_shav16qi3;
emit_insn (shift_insn (operands[0], operands[1], reg));
DONE;
@@ -11468,7 +11468,7 @@
if (negate)
emit_insn (gen_negv2di2 (reg, reg));
- emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg));
+ emit_insn (gen_xop_shav2di3 (operands[0], operands[1], reg));
DONE;
})
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 180650)
+++ config/i386/i386.c (working copy)
@@ -26538,14 +26538,14 @@ static const struct builtin_description bdesc_mult
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3,
"__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN,
(int)MULTI_ARG_2_SI_IMM },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3,
"__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN,
(int)MULTI_ARG_2_HI_IMM },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3,
"__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN,
(int)MULTI_ARG_2_QI_IMM },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3,
"__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN,
(int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3,
"__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN,
(int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3,
"__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN,
(int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3,
"__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN,
(int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3,
"__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN,
(int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3,
"__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN,
(int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3,
"__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN,
(int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3,
"__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN,
(int)MULTI_ARG_2_QI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3,
"__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN,
(int)MULTI_ARG_2_DI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3,
"__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN,
(int)MULTI_ARG_2_SI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3,
"__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN,
(int)MULTI_ARG_2_HI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3,
"__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN,
(int)MULTI_ARG_2_QI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3,
"__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN,
(int)MULTI_ARG_2_DI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3,
"__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN,
(int)MULTI_ARG_2_SI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3,
"__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN,
(int)MULTI_ARG_2_HI },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3,
"__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN,
(int)MULTI_ARG_2_QI },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2,
"__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN,
(int)MULTI_ARG_2_SF },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2,
"__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN,
(int)MULTI_ARG_2_DF },
