On Fri, Oct 28, 2011 at 8:21 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> Hello!
>
> We can extend existing code attributes. Also, the patch includes some
> stylistic changes in XOP shift patterns.
>
> No functional changes.
Eh, the patch was the old one, added is additional patch with updated ChangeLog:
2011-10-28 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (shift_insn): Rename code attribute from
shiftrt_insn. Also handle ashift RTX.
(shift): Rename code attribute from shiftrt. Also handle ashift RTX.
(vshift): New code attribute.
(<shift_insn>*): Rename from <shiftrt_insn>*. Update asm templates.
(any_lshift): Move and rename code iterator from ...
* config/i386/sse.md (lshift): ... here.
(lshift_insn): Remove code attribute.
(lshift): Remove code attribute.
(vlshr<mode>3): Use lshiftrt RTX.
(vashr<mode>3, ashrv16qi3, ashrv2di3): Use ashiftrt RTX.
(vashl<mode>3, ashlv16qi3): Use ashift RTX.
(avx2_<lshift>v<mode>): Rename from avx2_<shift_insn>v<mode>. Use
any_lshift code iterator. Update asm template.
(<shift_insn><mode>3): Macroize insn from lshr<mode>3 and ashl<mode>3
usign any_lshift code iterator.
* config/i386/mmx.md (mmx_<shift_insn><mode>3): Macroize insn from
mmx_lshr<mode>3 and mmx_ashl<mode>3 usign any_lshift code iterator.
* config/i386/i386.c (bdesc_args) <__builtin_ia32_psll>: Update.
Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32} and committed to mainline SVN.
Uros.
Index: i386.md
===================================================================
--- i386.md (revision 180622)
+++ i386.md (working copy)
@@ -772,6 +772,9 @@
;; Base name for insn mnemonic.
(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
+;; Mapping of logic-shift operators
+(define_code_iterator any_lshift [ashift lshiftrt])
+
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
@@ -781,6 +784,7 @@
;; Base name for insn mnemonic.
(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
+(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
;; Mapping of rotate operators
(define_code_iterator any_rotate [rotate rotatert])
Index: mmx.md
===================================================================
--- mmx.md (revision 180621)
+++ mmx.md (working copy)
@@ -1037,13 +1037,13 @@
(const_string "0")))
(set_attr "mode" "DI")])
-(define_insn "mmx_lshr<mode>3"
+(define_insn "mmx_<shift_insn><mode>3"
[(set (match_operand:MMXMODE248 0 "register_operand" "=y")
- (lshiftrt:MMXMODE248
+ (any_lshift:MMXMODE248
(match_operand:MMXMODE248 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "yN")))]
"TARGET_MMX"
- "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
+ "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
@@ -1051,20 +1051,6 @@
(const_string "0")))
(set_attr "mode" "DI")])
-(define_insn "mmx_ashl<mode>3"
- [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
- (ashift:MMXMODE248
- (match_operand:MMXMODE248 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "yN")))]
- "TARGET_MMX"
- "psll<mmxvecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "1")
- (const_string "0")))
- (set_attr "mode" "DI")])
-
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral comparisons
Index: sse.md
===================================================================
--- sse.md (revision 180622)
+++ sse.md (working copy)
@@ -167,9 +167,6 @@
(V4SI "vec") (V8SI "avx2")
(V2DI "vec") (V4DI "avx2")])
-;; Mapping of logic-shift operators
-(define_code_iterator any_lshift [ashift lshiftrt])
-
(define_mode_attr ssedoublemode
[(V16HI "V16SI") (V8HI "V8SI")])
@@ -5826,15 +5823,15 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn "lshr<mode>3"
+(define_insn "<shift_insn><mode>3"
[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
- (lshiftrt:VI248_AVX2
+ (any_lshift:VI248_AVX2
(match_operand:VI248_AVX2 1 "register_operand" "0,x")
(match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
"TARGET_SSE2"
"@
- psrl<ssemodesuffix>\t{%2, %0|%0, %2}
- vpsrl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
+ v<vshift><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
@@ -5845,25 +5842,6 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn "ashl<mode>3"
- [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
- (ashift:VI248_AVX2
- (match_operand:VI248_AVX2 1 "register_operand" "0,x")
- (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
- "TARGET_SSE2"
- "@
- psll<ssemodesuffix>\t{%2, %0|%0, %2}
- vpsll<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseishft")
- (set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "1")
- (const_string "0")))
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "<sseinsnmode>")])
-
(define_expand "vec_shl_<mode>"
[(set (match_operand:VI_128 0 "register_operand" "")
(ashift:V1TI
@@ -11406,9 +11384,10 @@
;; SSE2 doesn't have some shift varients, so define versions for XOP
(define_expand "ashlv16qi3"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand" "")
+ (ashift:V16QI
+ (match_operand:V16QI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
"TARGET_XOP"
{
rtvec vs = rtvec_alloc (16);
@@ -11442,9 +11421,10 @@
})
(define_expand "ashrv16qi3"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand" "")
+ (ashiftrt:V16QI
+ (match_operand:V16QI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
"TARGET_XOP"
{
rtvec vs = rtvec_alloc (16);
@@ -11473,9 +11453,10 @@
})
(define_expand "ashrv2di3"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V2DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")]
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (ashiftrt:V2DI
+ (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:DI 2 "nonmemory_operand" "")))]
"TARGET_XOP"
{
rtvec vs = rtvec_alloc (2);
