This is strictly an optimization patch. It adds flag setting variants
of key arithmetic, logical, extensions, shifts, etc. That in turn
allows the compare-elim pass to do its job.
At this point the v8 port is converted and should be functioning at the
same level it was before the conversion. As I noted in the cover
message, there are some further things that could be improved, the only
one I plan to look at is conversion to LRA.
Committed to the trunk.
Jeff
* config/v850/v850.md (addsi3_set_flags): New pattern.
(subsi3_set_flags, negsi2_set_flags, andsi3_set_flags): Likewise.
(iorsi3_set_flags, xorsi3_set_flags, one_cmplsi2_set_flags): Likewise.
(zero_extendhisi2_v850_set_flags): Likewise.
(zero_extendqisi2_v850_set_flags): Likewise.
(ashlsi3_set_flags, ashlsi3_v850e2_set_flags): Likewise.
(lshrsi3_set_flags, lshrsi3_v850e2_set_flags): Likewise.
(ashrsi3_set_flags, ashrsi3_v850e2_set_flags): Likewise.
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 3cfec74..b8f098b 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -569,6 +569,20 @@
addi %O2(%P2),%1,%0"
[(set_attr "length" "2,4,4")])
+(define_insn "addsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
+ (match_operand:SI 2 "nonmemory_operand"
"rJ,K,U"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ add %2,%0
+ addi %2,%1,%0
+ addi %O2(%P2),%1,%0"
+ [(set_attr "length" "2,4,4")])
+
;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------
@@ -593,6 +607,19 @@
subr %1,%0"
[(set_attr "length" "2,2")])
+(define_insn "*subsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ sub %2,%0
+ subr %1,%0"
+ [(set_attr "length" "2,2")])
+
(define_insn_and_split "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "0")))]
@@ -610,6 +637,16 @@
"subr %.,%0"
[(set_attr "length" "2")])
+(define_insn "*negsi2_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (neg:SI (match_operand:SI 1 "register_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_dup 1)))]
+ "reload_completed"
+ "subr %.,%0"
+ [(set_attr "length" "2")])
+
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------
@@ -831,6 +868,20 @@
andi %2,%1,%0"
[(set_attr "length" "2,2,4")])
+(define_insn "andsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (and:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ and %2,%0
+ and %.,%0
+ andi %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
+
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
@@ -916,6 +967,20 @@
ori %2,%1,%0"
[(set_attr "length" "2,2,4")])
+(define_insn "*iorsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ior:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ or %2,%0
+ or %.,%0
+ ori %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
+
;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
@@ -1001,6 +1066,20 @@
xori %2,%1,%0"
[(set_attr "length" "2,2,4")])
+(define_insn "*xorsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (xor:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ xor %2,%0
+ xor %.,%0
+ xori %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
+
;; ----------------------------------------------------------------------
;; NOT INSTRUCTIONS
@@ -1024,6 +1103,16 @@
"not %1,%0"
[(set_attr "length" "2")])
+(define_insn "*one_cmplsi2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (not:SI (match_operand:SI 1 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_dup 1)))]
+ "reload_completed"
+ "not %1,%0"
+ [(set_attr "length" "2")])
+
;; -----------------------------------------------------------------
;; BIT FIELDS
;; -----------------------------------------------------------------
@@ -1808,6 +1897,16 @@
"andi 65535,%1,%0"
[(set_attr "length" "4")])
+(define_insn "*zero_extendhisi2_v850_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (zero_extend:SI (match_operand:HI 1 "register_operand"
"r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_dup 1)))]
+ "reload_completed"
+ "andi 65535,%1,%0"
+ [(set_attr "length" "4")])
+
(define_expand "zero_extendhisi2"
[(parallel [(set (match_operand:SI 0 "register_operand")
(zero_extend:SI
@@ -1841,6 +1940,16 @@
"andi 255,%1,%0"
[(set_attr "length" "4")])
+(define_insn "*zero_extendqisi2_v850_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (zero_extend:SI (match_operand:QI 1 "register_operand"
"r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_dup 1)))]
+ "reload_completed"
+ "andi 255,%1,%0"
+ [(set_attr "length" "4")])
+
(define_expand "zero_extendqisi2"
[(parallel [(set (match_operand:SI 0 "register_operand")
(zero_extend:SI
@@ -1941,6 +2050,19 @@
shl %2,%0"
[(set_attr "length" "4,2")])
+(define_insn "ashlsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashift:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ shl %2,%0
+ shl %2,%0"
+ [(set_attr "length" "4,2")])
+
(define_insn "ashlsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI
@@ -1951,6 +2073,17 @@
"shl %2,%1,%0"
[(set_attr "length" "4")])
+(define_insn "ashlsi3_v850e2_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (ashift:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "shl %2,%1,%0"
+ [(set_attr "length" "4")])
+
(define_insn_and_split "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(lshiftrt:SI
@@ -1974,6 +2107,19 @@
shr %2,%0"
[(set_attr "length" "4,2")])
+(define_insn "lshrsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ shr %2,%0
+ shr %2,%0"
+ [(set_attr "length" "4,2")])
+
(define_insn "lshrsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI
@@ -1984,6 +2130,17 @@
"shr %2,%1,%0"
[(set_attr "length" "4")])
+(define_insn "lshrsi3_v850e2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "shr %2,%1,%0"
+ [(set_attr "length" "4")])
+
(define_insn_and_split "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ashiftrt:SI
@@ -2007,6 +2164,19 @@
sar %2,%0"
[(set_attr "length" "4,2")])
+(define_insn "ashrsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ sar %2,%0
+ sar %2,%0"
+ [(set_attr "length" "4,2")])
+
(define_insn "ashrsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI
@@ -2017,6 +2187,17 @@
"sar %2,%1,%0"
[(set_attr "length" "4")])
+(define_insn "ashrsi3_v850e2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "sar %2,%1,%0"
+ [(set_attr "length" "4")])
+
;; ----------------------------------------------------------------------
;; FIND FIRST BIT INSTRUCTION
;; ----------------------------------------------------------------------
