On Sat, Jun 23, 2018 at 03:26:50PM +0300, Dimitar Dimitrov wrote:
> I took arm/ldmstm.md as an inspiration. See attached machine description for
> PRU that requires the increase. I omitted this machine-generated MD file from
> my first patch set, but per comments will include it in v2.
>
> PRU has a total of 32 32-bit registers with flexible subregister addressing.
> The PRU GCC port represents the register file as 128 individual 8-bit
> registers. Rationale: http://gcc.gnu.org/ml/gcc/2017-01/msg00217.html
>
> Load/store instructions can load anywhere between 1 and 124 consecutive 8-bit
> registers. The load/store-multiple patterns seem to require const_int_operand
> offsets for each loaded register, hence the explosion of operands.
If it is consecutive only, then you could represent those that load a lot of
registers using wider modes, so represent e.g. that 124 register load as
15 DImode loads + 1 SImode.
Jakub
