Andre Simoes Dias Vieira <andre.simoesdiasvie...@arm.com> writes: > @@ -5716,10 +5717,17 @@ aarch64_classify_address (struct aarch64_address_info > *info, > unsigned int vec_flags = aarch64_classify_vector_mode (mode); > bool advsimd_struct_p = (vec_flags == (VEC_ADVSIMD | VEC_STRUCT)); > bool load_store_pair_p = (type == ADDR_QUERY_LDP_STP > + || type == ADDR_QUERY_LDP_STP_N > || mode == TImode > || mode == TFmode > || (BYTES_BIG_ENDIAN && advsimd_struct_p)); > > + /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode > + corresponds to the actual size of the memory being loaded/stored and the > + mode of the corresponding addressing mode is half of that. */ > + if (type == ADDR_QUERY_LDP_STP_N && known_eq (GET_MODE_SIZE (mode), 16)) > + mode = DFmode; > + > bool allow_reg_index_p = (!load_store_pair_p > && (known_lt (GET_MODE_SIZE (mode), 16) > || vec_flags == VEC_ADVSIMD
I don't know whether it matters in practice, but that description also applies to Umq, not just Uml. It might be worth changing it too so that things stay consistent. Thanks, Richard
