Hi Matthew,
> With one more change to add another comment as below, this is OK to
> commit.
>
> > @@ -18957,7 +19039,10 @@ mips_reorg_process_insns (void)
> > sequence and replace it with the delay slot instruction
> > then the jump to clear the forbidden slot hazard. */
>
> This bit does need the comment extending. Add this:
>
> For the P6600, this optimisation solves the performance penalty associated
> with BALC followed by a delay slot branch. We do not set fs_delay as we
> do not want the full logic of a forbidden slot; the penalty exists only
> against branches not the full class of forbidden slot instructions.
>
> >
> > - if (fs_delay)
> > + if (fs_delay || (TUNE_P6600
> > + && TARGET_CB_MAYBE
> > + && mips_classify_branch_p6600 (insn)
> > + == UC_BALC))
> > {
> > /* Search onwards from the current position looking for
> > a SEQUENCE. We are looking for pipeline hazards
> here
Added and committed as r261570.
Regards,
Robert
