Richard Sandiford wrote:
>> This has probably been reported elsewhere already but I can't find
>> such a report, so sorry for possible duplicate,
>> but this patch is causing ICEs on aarch64
>> FAIL: gcc.target/aarch64/sve/reduc_1.c -march=armv8.2-a+sve
>> (internal compiler error)
>> FAIL: gcc.target/aarch64/sve/reduc_5.c -march=armv8.2-a+sve
>> (internal compiler error)
>>
>> and also many scan-assembler regressions:
>>
>>
>> http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/260951/report-build-info.html
>
> Thanks for the heads-up. Looks like they're all SVE, so I'll take this.
It seems this is due to unnecessary spills of PR_REGS - the subset doesn't work
for those.
The original proposal doing:
if (allocno_class != POINTER_AND_FP_REGS)
return allocno_class;
doesn't appear to affect SVE. However the question is whether the register
allocator
can get confused about PR_REGS and end up with POINTER_AND_FP_REGS for
both the allocno_class and best_class? If so then the return needs to support
predicate
modes too.
Wilco
