Ping? Backport may not be appropriate but I'd still like it in trunk. > -----Original Message----- > From: gcc-patches-ow...@gcc.gnu.org <gcc-patches-ow...@gcc.gnu.org> > On Behalf Of Tamar Christina > Sent: Monday, April 30, 2018 15:13 > To: gcc-patches@gcc.gnu.org > Cc: nd <n...@arm.com>; James Greenhalgh <james.greenha...@arm.com>; > Richard Earnshaw <richard.earns...@arm.com>; Marcus Shawcroft > <marcus.shawcr...@arm.com> > Subject: [PATCH][GCC][AArch64] Correct 3 way XOR instructions adding > missing patterns. > > Hi All, > > This patch adds the missing neon intrinsics for all 128 bit vector Integer > modes for the three-way XOR and negate and xor instructions for Arm8.2-a > to Armv8.4-a. > > Bootstrapped and regtested on aarch64-none-linux-gnue and no issues. > > Ok for master? And for backport to the GCC-8 branch? > > gcc/ > 2018-04-30 Tamar Christina <tamar.christ...@arm.com> > > * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to > eor3q<mode>4. > (aarch64_bcaxqv8hi): Change to bcaxq<mode>4. > * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32, > veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, > vbcaxq_u8, > vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, > vbcaxq_s64): New. > * config/aarch64/arm_neon.h: Likewise. > * config/aarch64/iterators.md (VQ_I): New. > > gcc/testsuite/ > 2018-04-30 Tamar Christina <tamar.christ...@arm.com> > > * gcc.target/gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32, > veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, > vbcaxq_u8, > vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, > vbcaxq_s64): New. > * gcc.target/gcc.target/aarch64/sha3_1.c: Likewise. > * gcc.target/gcc.target/aarch64/sha3_1.c: Likewise. > * gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
Copy and paste wibble, will correct when committing. > > Thanks, > Tamar > > --
